Inventor
ZHOU TINGDONG
US28 patents
⚠️ This page may combine multiple inventors who share the name “ZHOU TINGDONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS9726691B2Aug 8, 2017
3D chip testing through micro-C4 interface
IBM24 citations91
US7533360B1May 12, 2009
Flow based package pin assignment
IBM11 citations84
US9141421B2Sep 22, 2015
Reducing power grid noise in a processor while minimizing performance loss
IBM8 citations83
US7863106B2Jan 4, 2011
Silicon interposer testing for three dimensional chip stack
IBM18 citations80
US9646925B2May 9, 2017
Interconnect array pattern with a 3:1 signal-to-ground ratio
IBM2 citations72
US9600619B2Mar 21, 2017
Distribution of power vias in a multi-layer circuit board
IBM2 citations72
US9543241B2Jan 10, 2017
Interconnect array pattern with a 3:1 signal-to-ground ratio
IBM3 citations72
US10371717B2Aug 6, 2019
3D chip testing through micro-C4 interface
IBM1 citations70
US9972566B2May 15, 2018
Interconnect array pattern with a 3:1 signal-to-ground ratio
IBM1 citations62
US9456498B2Sep 27, 2016
Electronic module power supply
IBM2 citations62
US11193953B2Dec 7, 2021
3D chip testing through micro-C4 interface
IBM0 citations60
US10765002B2Sep 1, 2020
Electronic module power supply
IBM0 citations51
US10362674B2Jul 23, 2019
Electronic module power supply
IBM0 citations51
US10080285B2Sep 18, 2018
Electronic module power supply
IBM0 citations51
US9594865B2Mar 14, 2017
Distribution of power vias in a multi-layer circuit board
IBM0 citations51
US9146772B2Sep 29, 2015
Reducing power grid noise in a processor while minimizing performance loss
IBM0 citations51
US7844925B2Nov 30, 2010
System and method for power domain optimization
IBM0 citations51
FREESCALE SEMICONDUCTOR INC
3 patentsUS9974174B1May 15, 2018
Package to board interconnect structure with built-in reference plane structure
FREESCALE SEMICONDUCTOR INC8 citations82
US10037970B2Jul 31, 2018
Multiple interconnections between die
FREESCALE SEMICONDUCTOR INC1 citations50
US10147654B2Dec 4, 2018
Package materials monitor and method therefor
FREESCALE SEMICONDUCTOR INC0 citations47
BECKER WIREN DALE
3 patentsUS8261226B1Sep 4, 2012
Network flow based module bottom surface metal pin assignment
BECKER WIREN DALE13 citations82
US8339803B2Dec 25, 2012
High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost
BECKER WIREN DALE2 citations60
US8683413B2Mar 25, 2014
Method for making high-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost
BECKER WIREN DALE0 citations50
NXP USA INC
3 patentsUS12341089B2Jun 24, 2025
Device package substrate structure and method therefor
NXP USA INC0 citations61
US11798871B2Oct 24, 2023
Device package substrate structure and method therefor
NXP USA INC0 citations61
US10537019B1Jan 14, 2020
Substrate dielectric crack prevention using interleaved metal plane
NXP USA INC1 citations56