Inventor

CHEN SHUI-HUNG

TW49 patents

⚠️ This page may combine multiple inventors who share the name “CHEN SHUI-HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN SHUI-HUNG

TAIWAN SEMICONDUCTOR MFG

STI process for improving isolation for deep sub-micron application

Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM

Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions

Method of manufacture of vertical stacked gate flash memory device

Vertical stacked gate flash memory device

Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance

Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM

Method of forming a metal gate for CMOS devices using a replacement gate process

Decoupling capacitor

Polycrystalline silicon diode string for ESD protection of different power supply connections

Flash memory cell with vertically oriented channel

Method of manufacture of vertical split gate flash memory device

Channel stop ion implantation method for CMOS integrated circuits

N-type structure for n-type pull-up and down I/O protection circuit

Modified source side inserted anti-type diffusion ESD protection device

Plasma damage protection cell using floating N/P/N and P/N/P structure

Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application

Robust latchup-immune CMOS structure

Method for forming mirror image split gate flash memory devices by forming a central source line slot

Method for forming vertical channel flash memory cell using P/N junction isolation

Method of manufacture of vertical split gate flash memory device

Flash memory cell with vertical channels, and source/drain bus lines

Method for forming vertical channel flash memory cell and device manufactured thereby

Highly latchup-immune CMOS I/O structures

Method of manufacturing a highly latchup-immune CMOS I/O structure

Integrated circuit having improved ESD protection

Integration method for deep sub-micron dual gate transistor design

ESD protection component

Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application

Diode for power protection

Integrated circuit having improved ESD protection

Modified source side inserted anti-type diffusion ESD protection device

Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor

Decoupling capacitor

Multi-level (4state/2-bit) stacked gate flash memory cell

Split gate flash memory device with source line

Method of delta-channel in deep sub-micron process

Flash memory cell with vertical channels, and source/drain bus lines

Whole chip ESD protection

Input/output devices with robustness of ESD protection

ESD protection circuit and method

Extended length metal line for improved ESD performance

Whole chip ESD protection

Whole chip ESD protection

Electrostatic discharge protection pattern for high voltage applications

Deep well implant structure providing latch-up resistant CMOS semiconductor product

String contact structure for high voltage ESD

ESD structure for high voltage ESD protection

TAIWAN SEMICONDUCTOR MANUFACTO

Multi-level (4 state/2-bit) stacked gate flash memory cell