Inventor
BAUER MARK E
US19 patents
⚠️ This page may combine multiple inventors who share the name “BAUER MARK E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS5508958AApr 16, 1996
Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage
INTEL CORP266 citations99
US5539690AJul 23, 1996
Write verify schemes for flash memory with multilevel cells
INTEL CORP314 citations98
US5485422AJan 16, 1996
Drain bias multiplexing for multiple bit flash cell
INTEL CORP223 citations98
US5822256AOct 13, 1998
Method and circuitry for usage of partially functional nonvolatile memory
INTEL CORP203 citations96
US6483742B1Nov 19, 2002
Bit map addressing schemes for flash memory
INTEL CORP40 citations95
US6097637AAug 1, 2000
Dynamic single bit per cell to multiple bit per cell memory
INTEL CORP109 citations95
US5828616AOct 27, 1998
Sensing scheme for flash memory with multilevel cells
INTEL CORP71 citations95
US5748546AMay 5, 1998
Sensing scheme for flash memory with multilevel cells
INTEL CORP62 citations95
US5497354AMar 5, 1996
Bit map addressing schemes for flash memory
INTEL CORP56 citations95
US5438546AAug 1, 1995
Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories
INTEL CORP78 citations94
US6772273B1Aug 3, 2004
Block-level read while write method and apparatus
INTEL CORP24 citations92
US5796667AAug 18, 1998
Bit map addressing schemes for flash memory
INTEL CORP27 citations92
US5781472AJul 14, 1998
Bit map addressing schemes for flash/memory
INTEL CORP22 citations92
US5663923ASep 2, 1997
Nonvolatile memory blocking architecture
INTEL CORP61 citations92
US5754566AMay 19, 1998
Method and apparatus for correcting a multilevel cell memory by using interleaving
INTEL CORP72 citations91
US5274278ADec 28, 1993
High-speed tri-level decoder with dual-voltage isolation
INTEL CORP21 citations90
US5815443ASep 29, 1998
Bit map addressing schemes for flash memory
INTEL CORP12 citations81
US5517138AMay 14, 1996
Dual row selection using multiplexed tri-level decoder
INTEL CORP12 citations72