Inventor
GOLLIVER ROGER
US20 patents
⚠️ This page may combine multiple inventors who share the name “GOLLIVER ROGER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS6105047AAug 15, 2000
Method and apparatus for trading performance for precision when processing denormal numbers in a computer system
INTEL CORP58 citations96
US5886915AMar 23, 1999
Method and apparatus for trading performance for precision when processing denormal numbers in a computer system
INTEL CORP26 citations92
US6243734B1Jun 5, 2001
Computer product and method for sparse matrices
INTEL CORP39 citations88
US10067680B2Sep 4, 2018
Methods and apparatus to manage workload memory allocation
INTEL CORP4 citations83
US9823850B2Nov 21, 2017
Methods and apparatus to manage workload memory allocation
INTEL CORP7 citations83
US9361217B2Jun 7, 2016
Methods and apparatus to manage workload memory allocation
INTEL CORP6 citations83
US11385793B2Jul 12, 2022
Methods and apparatus to manage workload memory allocation
INTEL CORP1 citations72
US10649662B2May 12, 2020
Methods and apparatus to manage workload memory allocation
INTEL CORP2 citations72
US11822789B2Nov 21, 2023
Methods and apparatus to manage workload memory allocation
INTEL CORP0 citations61
US9612951B2Apr 4, 2017
Methods and apparatus to manage workload memory allocation
INTEL CORP1 citations61
INST THE DEV OF EMERGING ARCHI
4 patentsUS6151669ANov 21, 2000
Methods and apparatus for efficient control of floating-point status register
INST THE DEV OF EMERGING ARCHI122 citations97
US6578059B1Jun 10, 2003
Methods and apparatus for controlling exponent range in floating-point calculations
INST THE DEV OF EMERGING ARCHI20 citations92
US6370639B1Apr 9, 2002
Processor architecture having two or more floating-point status fields
INST THE DEV OF EMERGING ARCHI23 citations92
US6212539B1Apr 3, 2001
Methods and apparatus for handling and storing bi-endian words in a floating-point processor
INST THE DEV OF EMERGING ARCHI13 citations73
WIEDEMEIER JEFF
3 patentsUS9141386B2Sep 22, 2015
Vector logical reduction operation implemented using swizzling on a semiconductor chip
WIEDEMEIER JEFF10 citations81
US8667042B2Mar 4, 2014
Functional unit for vector integer multiply add instruction
WIEDEMEIER JEFF13 citations81
US9092213B2Jul 28, 2015
Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation
WIEDEMEIER JEFF2 citations60