Inventor

MUHICH JOHN STEPHEN

US37 patents

⚠️ This page may combine multiple inventors who share the name “MUHICH JOHN STEPHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUHICH JOHN STEPHEN

IBM

Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching

Issuing instructions in a processor supporting out-of-order execution

Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched

Data processing system having memory sub-array redundancy and method therefor

Method and apparatus for phase rotation in a phase locked loop

Method and apparatus for coupled phase locked loops

System and method for controlling a memory array in an information handling system

Method and system for building a multiprocessor data processing system

Apparatus and method for facilitating out-of-order execution of load instructions

Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution

Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction

Support for out-of-order execution of loads and stores in a processor

Dispatching instructions in a processor supporting out-of-order execution

Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages

Method and apparatus for condensed history buffer

Method and apparatus for improved recovery of processor state using history buffer

Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory

High Speed SRAM with or-gate sense

Method and system for achieving atomic memory references in a multilevel cache data processing system

Fast read domino SRAM

Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length

Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization

Cache sub-array method and apparatus for use in microprocessor integrated circuits

Apparatus and method for processing multiple cache misses to a single cache line

Apparatus and method for instruction fetching using a multi-port instruction cache directory

Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator

Circuitry and method for latching information

System for reordering of instructions before placement into cache to reduce dispatch latency

Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding

Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging

Comparator circuit using two bit to four bit encoder

Dynamic expansion of execution pipeline stages

Adder circuit and method therefor

Circuitry and method for gating information

Mechanism for queuing store data and method therefor

Method and apparatus for fast parallel determination of queue entries

INTERNATIIONAL BUSINESS MACHIN

Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits