Inventor
RAO KAMESWARA K
US38 patents
⚠️ This page may combine multiple inventors who share the name “RAO KAMESWARA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
29 patentsUS7117373B1Oct 3, 2006
Bitstream for configuring a PLD with encrypted design data
XILINX INC65 citations98
US7098689B1Aug 29, 2006
Disabling unused/inactive resources in programmable logic devices for static power reduction
XILINX INC79 citations98
US6931543B1Aug 16, 2005
Programmable logic device with decryption algorithm and decryption key
XILINX INC114 citations98
US6366117B1Apr 2, 2002
Nonvolatile/battery-backed key in PLD
XILINX INC126 citations98
US6208549B1Mar 27, 2001
One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS
XILINX INC98 citations98
US6044012AMar 28, 2000
Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process
XILINX INC81 citations96
US5949987ASep 7, 1999
Efficient in-system programming structure and method for non-volatile programmable logic devices
XILINX INC81 citations96
US5689516ANov 18, 1997
Reset circuit for a programmable logic device
XILINX INC54 citations96
US5661685AAug 26, 1997
Programmable logic device with configurable power supply
XILINX INC95 citations94
US7562332B1Jul 14, 2009
Disabling unused/inactive resources in programmable logic devices for static power reduction
XILINX INC13 citations93
US7504854B1Mar 17, 2009
Regulating unused/inactive resources in programmable logic devices for static power reduction
XILINX INC29 citations93
US6243294B1Jun 5, 2001
Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process
XILINX INC25 citations93
US6177830B1Jan 23, 2001
High voltage charge pump using standard sub 0.35 micron CMOS process
XILINX INC38 citations93
US6055205AApr 25, 2000
Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process
XILINX INC42 citations93
US5959885ASep 28, 1999
Non-volatile memory array using single poly EEPROM in standard CMOS process
XILINX INC20 citations93
US5949712ASep 7, 1999
Non-volatile memory array using gate breakdown structure
XILINX INC48 citations93
US5835402ANov 10, 1998
Non-volatile storage for standard CMOS integrated circuits
XILINX INC47 citations93
US5523971AJun 4, 1996
Non-volatile memory cell for programmable logic device
XILINX INC40 citations93
US7581124B1Aug 25, 2009
Method and mechanism for controlling power consumption of an integrated circuit
XILINX INC50 citations92
US6549458B1Apr 15, 2003
Non-volatile memory array using gate breakdown structures
XILINX INC25 citations92
US6522582B1Feb 18, 2003
Non-volatile memory array using gate breakdown structures
XILINX INC20 citations92
US6265266B1Jul 24, 2001
Method of forming a two transistor flash EPROM cell
XILINX INC44 citations92
US5991880ANov 23, 1999
Overridable data protection mechanism for PLDs
XILINX INC25 citations92
US5914514AJun 22, 1999
Two transistor flash EPROM cell
XILINX INC47 citations92
US5838901ANov 17, 1998
Overridable data protection mechanism for PLDs
XILINX INC40 citations92
US5764076AJun 9, 1998
Circuit for partially reprogramming an operational programmable logic device
XILINX INC40 citations92
US7046071B1May 16, 2006
Series capacitor coupling multiplexer for programmable logic devices
XILINX INC13 citations84
US6438065B1Aug 20, 2002
Redundancy architecture and method for non-volatile storage
XILINX INC14 citations84
US7549139B1Jun 16, 2009
Tuning programmable logic devices for low-power design implementation
XILINX INC18 citations83