Inventor
LOVELACE JOHN V
US29 patents
⚠️ This page may combine multiple inventors who share the name “LOVELACE JOHN V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS7305668B2Dec 4, 2007
Secure method to perform computer system firmware updates
INTEL CORP80 citations95
US7213152B1May 1, 2007
Modular bios update mechanism
INTEL CORP57 citations94
US9025399B1May 5, 2015
Method for training a control signal based on a strobe signal in a memory module
INTEL CORP36 citations92
US6564317B1May 13, 2003
Method and apparatus for securing computer firmware wherein unlocking of nonvolatile memory is prohibited unless address line masking Is disabled during an initialization event
INTEL CORP20 citations92
US7036007B2Apr 25, 2006
Firmware architecture supporting safe updates and multiple processor types
INTEL CORP38 citations89
US10347319B2Jul 9, 2019
Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
INTEL CORP5 citations83
US9373365B2Jun 21, 2016
Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
INTEL CORP4 citations83
US9330734B2May 3, 2016
Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
INTEL CORP9 citations83
US10148416B2Dec 4, 2018
Signal phase optimization in memory interface training
INTEL CORP8 citations82
US9627029B2Apr 18, 2017
Method for training a control signal based on a strobe signal in a memory module
INTEL CORP9 citations82
US6591352B2Jul 8, 2003
Method and apparatus for executing firmware from a valid startup block
INTEL CORP14 citations82
US7949850B2May 24, 2011
Methods and appratus for demand-based memory mirroring
INTEL CORP9 citations81
US9852021B2Dec 26, 2017
Method and apparatus for encoding registers in a memory module
INTEL CORP3 citations80
US7107405B2Sep 12, 2006
Writing cached data to system management memory
INTEL CORP10 citations74
US10891243B2Jan 12, 2021
Memory bus MR register programming process
INTEL CORP4 citations72
US10380043B2Aug 13, 2019
Memory bus MR register programming process
INTEL CORP2 citations72
US7765409B2Jul 27, 2010
Modular BIOS update mechanism
INTEL CORP6 citations70
US10621121B2Apr 14, 2020
Measurement and optimization of command signal timing margins
INTEL CORP3 citations69
US12531098B2Jan 20, 2026
Memory module based data buffer communication bus training
INTEL CORP0 citations59
US12321622B2Jun 3, 2025
Deferred ECC (error checking and correction) memory initialization by memory scrub hardware
INTEL CORP0 citations51
US10552643B2Feb 4, 2020
Fast boot up memory controller
INTEL CORP0 citations51
US10289431B2May 14, 2019
Technologies for reduced control and status register access latency
INTEL CORP0 citations37