Inventor

HUANG JENN MING

TW65 patents

Patents

50 patents

US6187624B1Feb 13, 2001

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

TAIWAN SEMICONDUCTOR MFG94 citations98

US6117725ASep 12, 2000

Method for making cost-effective embedded DRAM structures compatible with logic circuit processing

TAIWAN SEMICONDUCTOR MFG89 citations98

US6100118AAug 8, 2000

Fabrication of metal fuse design for redundancy technology having a guard ring

TAIWAN SEMICONDUCTOR MFG116 citations98

US6096595AAug 1, 2000

Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices

TAIWAN SEMICONDUCTOR MFG101 citations98

US6042999AMar 28, 2000

Robust dual damascene process

TAIWAN SEMICONDUCTOR MFG120 citations98

US6037222AMar 14, 2000

Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology

TAIWAN SEMICONDUCTOR MFG148 citations98

US6353269B1Mar 5, 2002

Method for making cost-effective embedded DRAM structures compatible with logic circuit processing

TAIWAN SEMICONDUCTOR MFG56 citations96

US6255160B1Jul 3, 2001

Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells

TAIWAN SEMICONDUCTOR MFG80 citations96

US6198173B1Mar 6, 2001

SRAM with improved Beta ratio

TAIWAN SEMICONDUCTOR MFG50 citations96

US6157064ADec 5, 2000

Method and a deep sub-micron field effect transistor structure for suppressing short channel effects

TAIWAN SEMICONDUCTOR MFG71 citations96

US6127260AOct 3, 2000

Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices

TAIWAN SEMICONDUCTOR MFG70 citations96

US6074908AJun 13, 2000

Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits

TAIWAN SEMICONDUCTOR MFG84 citations96

US6033963AMar 7, 2000

Method of forming a metal gate for CMOS devices using a replacement gate process

TAIWAN SEMICONDUCTOR MFG225 citations96

US5989966ANov 23, 1999

Method and a deep sub-micron field effect transistor structure for suppressing short channel effects

TAIWAN SEMICONDUCTOR MFG53 citations96

US5918120AJun 29, 1999

Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines

TAIWAN SEMICONDUCTOR MFG85 citations96

US5863820AJan 26, 1999

Integration of sac and salicide processes on a chip having embedded memory

TAIWAN SEMICONDUCTOR MFG81 citations96

US6617631B2Sep 9, 2003

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

TAIWAN SEMICONDUCTOR MFG23 citations93

US6579784B1Jun 17, 2003

Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers

TAIWAN SEMICONDUCTOR MFG38 citations93

US6436763B1Aug 20, 2002

Process for making embedded DRAM circuits having capacitor under bit-line (CUB)

TAIWAN SEMICONDUCTOR MFG39 citations93

US6406987B1Jun 18, 2002

Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions

TAIWAN SEMICONDUCTOR MFG43 citations93

US6351016B1Feb 26, 2002

Technology for high performance buried contact and tungsten polycide gate integration

TAIWAN SEMICONDUCTOR MFG19 citations93

US6274471B1Aug 14, 2001

Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique

TAIWAN SEMICONDUCTOR MFG41 citations93

US6251726B1Jun 26, 2001

Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar

TAIWAN SEMICONDUCTOR MFG54 citations93

US6235593B1May 22, 2001

Self aligned contact using spacers on the ILD layer sidewalls

TAIWAN SEMICONDUCTOR MFG50 citations93

US6137179AOct 24, 2000

Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines

TAIWAN SEMICONDUCTOR MFG18 citations93

US6117723ASep 12, 2000

Salicide integration process for embedded DRAM devices

TAIWAN SEMICONDUCTOR MFG46 citations93

US6103622AAug 15, 2000

Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device

TAIWAN SEMICONDUCTOR MFG25 citations93

US6100116AAug 8, 2000

Method to form a protected metal fuse

TAIWAN SEMICONDUCTOR MFG51 citations93

US6025279AFeb 15, 2000

Method of reducing nitride and oxide peeling after planarization using an anneal

TAIWAN SEMICONDUCTOR MFG34 citations93

US6015730AJan 18, 2000

Integration of SAC and salicide processes by combining hard mask and poly definition

TAIWAN SEMICONDUCTOR MFG54 citations93

US6004843ADec 21, 1999

Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip

TAIWAN SEMICONDUCTOR MFG46 citations93

US5998252ADec 7, 1999

Method of salicide and sac (self-aligned contact) integration

TAIWAN SEMICONDUCTOR MFG53 citations93

US5924011AJul 13, 1999

Silicide process for mixed mode product

TAIWAN SEMICONDUCTOR MFG17 citations93

US5918119AJun 29, 1999

Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure

TAIWAN SEMICONDUCTOR MFG20 citations93

US5899722AMay 4, 1999

SOI device for DRAM cells beyond gigabit generation and method for making the same

TAIWAN SEMICONDUCTOR MFG17 citations84

US6001721ADec 14, 1999

Silicide and salicide on the same chip

TAIWAN SEMICONDUCTOR MFG19 citations84

US5494843AFeb 27, 1996

Method for forming MOSFET devices

TAIWAN SEMICONDUCTOR MFG20 citations84

US7030440B2Apr 18, 2006

Single poly-si process for DRAM by deep N-well (NW) plate

TAIWAN SEMICONDUCTOR MFG10 citations74

US6294456B1Sep 25, 2001

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

TAIWAN SEMICONDUCTOR MFG9 citations74

US6103621AAug 15, 2000

Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device

TAIWAN SEMICONDUCTOR MFG13 citations74

US6015735AJan 18, 2000

Method for forming a multi-anchor DRAM capacitor and capacitor formed

TAIWAN SEMICONDUCTOR MFG13 citations74

US5998269ADec 7, 1999

Technology for high performance buried contact and tungsten polycide gate integration

TAIWAN SEMICONDUCTOR MFG10 citations74

Showing the top 50 of 65 patents by PatentIndex Score.

HUANG JENN MING

Patents

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

Method for making cost-effective embedded DRAM structures compatible with logic circuit processing

Fabrication of metal fuse design for redundancy technology having a guard ring

Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices

Robust dual damascene process

Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology

Method for making cost-effective embedded DRAM structures compatible with logic circuit processing

Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells

SRAM with improved Beta ratio

Method and a deep sub-micron field effect transistor structure for suppressing short channel effects

Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices

Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits

Method of forming a metal gate for CMOS devices using a replacement gate process

Method and a deep sub-micron field effect transistor structure for suppressing short channel effects

Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines

Integration of sac and salicide processes on a chip having embedded memory

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers

Process for making embedded DRAM circuits having capacitor under bit-line (CUB)

Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions

Technology for high performance buried contact and tungsten polycide gate integration

Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique

Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar

Self aligned contact using spacers on the ILD layer sidewalls

Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines

Salicide integration process for embedded DRAM devices

Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device

Method to form a protected metal fuse

Method of reducing nitride and oxide peeling after planarization using an anneal

Integration of SAC and salicide processes by combining hard mask and poly definition

Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip

Method of salicide and sac (self-aligned contact) integration

Silicide process for mixed mode product

Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure

Method of forming dual spacer for self aligned contact integration

Method of improving beta ratio in SRAM and device manufactured thereby

Robust method of forming a cylinder capacitor for DRAM circuits

Method for forming a cylindrical capacitor in DRAM having pin plug profile

Overlay measurement improvement between damascene metal interconnections

Single poly-Si process for DRAM by deep N well (NW) plate

Approach for self-aligned contact and pedestal

Well-controlled CMP process for DRAM technology

SOI device for DRAM cells beyond gigabit generation and method for making the same

Silicide and salicide on the same chip

Method for forming MOSFET devices

Single poly-si process for DRAM by deep N-well (NW) plate

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device

Method for forming a multi-anchor DRAM capacitor and capacitor formed

Technology for high performance buried contact and tungsten polycide gate integration