Inventor
HANAFI HUSSEIN IBRAHIM
US17 patents
⚠️ This page may combine multiple inventors who share the name “HANAFI HUSSEIN IBRAHIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS6337497B1Jan 8, 2002
Common source transistor capacitor stack
IBM100 citations98
US6077745AJun 20, 2000
Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
IBM277 citations98
US6040210AMar 21, 2000
2F-square memory cell for gigabit memory applications
IBM101 citations98
US6034389AMar 7, 2000
Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
IBM154 citations98
US5874760AFeb 23, 1999
4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
IBM240 citations98
US6271094B1Aug 7, 2001
Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
IBM245 citations97
US6013548AJan 11, 2000
Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
IBM99 citations97
US5929477AJul 27, 1999
Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
IBM192 citations96
US6093947AJul 25, 2000
Recessed-gate MOSFET with out-diffused source/drain extension
IBM80 citations95
US6033957AMar 7, 2000
4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
IBM81 citations95
US6440808B1Aug 27, 2002
Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly
IBM48 citations91
US6245619B1Jun 12, 2001
Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devices
IBM51 citations91
US6218236B1Apr 17, 2001
Method of forming a buried bitline in a vertical DRAM device
IBM36 citations91
US6686630B2Feb 3, 2004
Damascene double-gate MOSFET structure and its fabrication method
IBM44 citations89
US6063699AMay 16, 2000
Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets
IBM15 citations73
US5759920AJun 2, 1998
Process for making doped polysilicon layers on sidewalls
IBM15 citations73