Inventor

BRACERAS GEORGE M

US53 patents

⚠️ This page may combine multiple inventors who share the name “BRACERAS GEORGE M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRACERAS GEORGE M

IBM

Structure for power-efficient cache memory

Adaptive integrated circuit based on transistor current measurements

Active restore weak write test mode

Memory cells with read access schemes

System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture

Apparatus and method for improved SRAM device performance through double gate topology

BIST circuit for variable impedance system

Method and apparatus for programmable active termination of input/output devices

Dynamic dielectric protection circuit for a receiver

Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests

Off-chip driver circuits

Efficient semiconductor burn-in circuit and method of operation

Functional pipelined virtual multiport cache memory with plural access during a single cycle

Column selectable self-biasing virtual voltages for SRAM write assist

Content addressable memory structure

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Delay-lock-loop with improved accuracy and range

Method and apparatus for improving cycle time in a quad data rate SRAM device

Active restore weak write test mode

Boost control to improve SRAM write operation

Apparatus for improved SRAM device performance through double gate topology

Scalable termination

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

Adaptive integrated circuit based on transistor current measurements

Method for margin testing

Page boundary caches

Two stage sensing for large static memory arrays

Output latching circuit for static memory devices

Content addressable memory for a data processing system

Redundant memory array having dual-use repair elements

Circuit to improve SRAM stability

Circuit and method for controlling a standby voltage level of a memory

Design structure for a current control mechanism for power networks and dynamic logic keeper circuits

Apparatus for implementing dynamic data path with interlocked keeper and restore devices

Dynamic precharge decode scheme for fast DRAM

Read only memory (ROM) with redundancy

Structure and method of alternating precharge in dynamic SOI circuits

GLOBALFOUNDRIES INC

Data aware write scheme for SRAM

Intracycle bitline restore in high performance memory

High performance sense amplifier

Column-dependent positive voltage boost for memory cell supply voltage

Sense amplifiers and multiplexed latches

Address based memory data path programming scheme

ADAMS CHAD A

Apparatus and method for implementing write assist for static random access memory arrays

Single supply sub VDD bit-line precharge SRAM and method for level shifting

BRACERAS GEORGE M

Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

Read only memory (ROM) with redundancy

ARSOVSKI IGOR

Vdiff max limiter in SRAMs for improved yield and power

Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability

MARVELL INT LTD

Multi-port high performance memory