Inventor

DALTON TIMOTHY J

US122 patents

⚠️ This page may combine multiple inventors who share the name “DALTON TIMOTHY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DALTON TIMOTHY J

IBM

Very low effective dielectric constant interconnect structures and methods for fabricating the same

Post metalization chem-mech polishing dielectric etch

Method of forming barrier layers for damascene interconnects

Dual etch stop/diffusion barrier for damascene interconnects

Very low effective dielectric constant interconnect Structures and methods for fabricating the same

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

Interconnect structures containing stress adjustment cap layer

Closed air gap interconnect structure

Copper recess process with application to selective capping and electroless plating

Process for forming a damascene structure

Extended gate sensor for pH sensing

Device and methodology for reducing effective dielectric constant in semiconductor devices

Protective hardmask for producing interconnect structures

Micro-cavity MEMS device and method of fabricating same

High density planar magnetic domain wall memory apparatus

Device and methodology for reducing effective dielectric constant in semiconductor devices

Structure for stochastic integrated circuit personalization

Structure and method for self aligned vertical plate capacitor

Air gap under on-chip passive device

Method of forming high density planar magnetic domain wall memory

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics

MIM capacitor and method of fabricating same

Interconnect structure improvements

Damascene interconnect structures including etchback for low-k dielectric materials

Trilayer resist scheme for gate etching applications

Method of forming closed air gap interconnects and structures formed thereby

Method of forming closed air gap interconnects and structures formed thereby

Copper recess process with application to selective capping and electroless plating

Fuse structure and method to form the same

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

On-chip decoupling capacitor with bottom hardmask

Fine-pitch device lithography using a sacrificial hardmask

Device and methodology for reducing effective dielectric constant in semiconductor devices

High density planar magnetic domain wall memory apparatus

Interconnect structures with encasing cap and methods of making thereof

Flash memory gate structure for widened lithography window

Semitubular metal-oxide-semiconductor field effect transistor

Addressable hierarchical metal wire test methodology

Electrical fuses and resistors having sublithographic dimensions

Chip-in-slot interconnect for 3D chip stacks

Method and structure for forming slot via bitline for MRAM devices

MASSACHUSETTS INST TECHNOLOGY

Apparatus and method for real-time measurement of thin film layer thickness and changes thereof

EDELSTEIN DANIEL C

Reducing effective dielectric constant in semiconductor devices

FULLER NICHOLAS C

Trilayer resist scheme for gate etching applications

INFINEON TECHNOLOGIES AG

Back end interconnect with a shaped interface

DIGITAL EQUIPMENT CORP

Methodology for in situ etch stop detection and control of plasma etching process and device design to minimize process chamber contamination

BLACK CHARLES T

Pattern formation employing self-assembled material

BERNSTEIN KERRY

Three dimensional vertical E-fuse structures and methods of manufacturing the same

YANG CHIH-CHAO

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application