Inventor

DUVVURY CHARVAKA

US74 patents

⚠️ This page may combine multiple inventors who share the name “DUVVURY CHARVAKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUVVURY CHARVAKA

TEXAS INSTRUMENTS INC

Efficient ESD protection with application for low capacitance I/O pads

Drain-extended MOS ESD protection structure

EOS/ESD protection for high density integrated circuits

Semiconductor ESD protection circuit

Silicon controlled rectifier and method for forming the same

Efficient ESD input protection scheme

Output buffer with improved ESD protection

Gate coupled SCR for ESD protection circuits

Lateral DMOS design for ESD protection

Minimization and linearization of ESD parasitic capacitance in integrated circuits

Semiconductor ESD protection circuit

Power device integration for built-in ESD robustness

Method for forming a silicon controlled rectifier

MOS device with substrate potential elevation

Output buffer and I/O protection circuit for CMOS technology

Drain-extended MOS ESD protection structure

Device and method of low voltage SCR protection for high voltage failsafe ESD applications

ESD protection circuit for advanced technologies

High voltage trigger remote-cathode SCR

Semiconductor ESD protection circuit

Protection circuit for output drivers

Bimodal ESD protection for DRAM power supplies and SCRs for DRAMs and logic circuits

PNP punchthrough-assisted protection device for special applications in CMOS technologies

Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

ESD/EOS protection circuits for integrated circuits

Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

CMOS sense amplifier

CMOS sense amplifier with bit line isolation

PNP driven NMOS ESD protection circuit

Semiconductor device with protection circuitry and method

ESD protection circuit for dual 3V/5V supply devices using single thickness gate oxides

Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors

Low resistance input protection circuit

Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection

Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection

Depletion controlled isolation stage

Integrated circuit design error detector for electrostatic discharge and latch-up applications

Electrostatic discharge protection device including precharge reduction

Device and method of low voltage SCR protection for high voltage failsafe ESD applications

Integrated ESD protection circuit using a substrate triggered lateral NPN

Guardwall structures for ESD protection

ESD protection for RF power amplifier circuits

In package ESD protections of IC using a thin film polymer

Sense amplifier with reduced instantaneous power

CMOS sense amplifier with N-channel sensing

Semiconductor dual guardring arrangement

Local ESD protection for low-capacitance applications

Body-biased pMOS protection against electrostatic discharge

Substrate pump ESD protection for silicon-on-insulator technologies

UNIV ILLINOIS

Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein