Inventor
GAUTHIER ROBERT J
US17 patents
⚠️ This page may combine multiple inventors who share the name “GAUTHIER ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS6411480B1Jun 25, 2002
Substrate pumped ESD network with trench structure
IBM29 citations92
US6097069AAug 1, 2000
Method and structure for increasing the threshold voltage of a corner device
IBM47 citations92
US8760831B2Jun 24, 2014
Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
IBM6 citations84
US7645676B2Jan 12, 2010
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
IBM8 citations84
US7098513B2Aug 29, 2006
Low trigger voltage, low leakage ESD NFET
IBM11 citations84
US8803276B2Aug 12, 2014
Electrostatic discharge (ESD) device and method of fabricating
IBM6 citations83
US8637388B2Jan 28, 2014
Semiconductor device heat dissipation structure
IBM12 citations82
US6136656AOct 24, 2000
Method to create a depleted poly MOSFET
IBM9 citations74
US7709926B2May 4, 2010
Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit
IBM3 citations63
US6838323B2Jan 4, 2005
Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure
IBM5 citations63
US7700428B2Apr 20, 2010
Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory
IBM0 citations52
US6171918B1Jan 9, 2001
Depleted poly mosfet structure and method
IBM0 citations52
US10181463B2Jan 15, 2019
Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
IBM0 citations51