Inventor

HIGASHITANI MASAAKI

US262 patents

⚠️ This page may combine multiple inventors who share the name “HIGASHITANI MASAAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HIGASHITANI MASAAKI

SANDISK TECHNOLOGIES INC

3D NAND with oxide semiconductor channel

Three-dimensional memory device having a transition metal dichalcogenide channel

NAND boosting using dynamic ramping of word line voltages

Memory cell with high-k charge trapping layer

Three-dimensional memory device having a heterostructure quantum well channel

3D memory having crystalline silicon NAND string channel

Dynamic erase voltage step size selection for 3D non-volatile memory

3D non-volatile storage with wide band gap transistor decoder

Dynamic erase depth for improved endurance of non-volatile memory

Compensation for temperature dependence of bit line resistance

Thin film transistor

Bit line and compare voltage modulation for sensing nonvolatile storage elements

3D non-volatile storage with transistor decoding structure

Fabricating 3D non-volatile storage with transistor decoding structure

Method and apparatus for program and erase of select gate transistors

Integrated nanostructure-based non-volatile memory fabrication

SANDISK CORP

Source side self boosting technique for non-volatile memory

Source side self boosting technique for non-volatile memory

Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells

Selective application of program inhibit schemes in non-volatile memory

Boosting methods for NAND flash memory

Use of voids between elements in semiconductor structures for isolation

Methods of forming integrated circuit devices using composite spacer structures

Data state-based temperature compensation during sensing in non-volatile memory

Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation

Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation

Use of voids between elements in semiconductor structures for isolation

Flash devices with shared word lines

Selective program voltage ramp rates in non-volatile memory

NAND flash memory with boosting

Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same

Metal contact via structure surrounded by an air gap and method of making thereof

Multiple liner interconnects for three dimensional memory devices and method of making thereof

Offset backside contact via structures for a three-dimensional memory device

Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof

Inter-plane offset in backside contact via structures for a three-dimensional memory device

Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof

3D NAND with partial block erase

HIGASHITANI MASAAKI

3D non-volatile memory with metal silicide interconnect

Method for fabricating passive devices for 3D non-volatile memory

Passive devices for 3D non-volatile memory

ADVANCED MICRO DEVICES INC

Sidewall NROM and method of manufacture thereof for non-volatile memory cells

FUJITSU LTD

Semiconductor memory of xN type having error correcting circuit by parity

LI HAIBO

Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device

SAMACHISA GEORGE

Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

SANDISK 3D LLC

Vertical bit line wide band gap TFT decoder

COSTA XIYING

Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current

MOKHLESI NIMA

Programming non-volatile storage with synchronized coupling