Inventor

TRAN JONATHAN (SON) HUNG

US21 patents

⚠️ This page may combine multiple inventors who share the name “TRAN JONATHAN (SON) HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN JONATHAN (SON) HUNG

TEXAS INSTRUMENTS INC

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Transposing a matrix using a streaming engine

Storage organization for transposing a matrix using a streaming engine

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Mechanism to queue multiple streams to run on streaming engine

Cache preload operations using streaming engine

Cache management operations using streaming engine

Cache preload operations using streaming engine

Cache management operations using streaming engine

Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors

Cache preload operations using streaming engine

Cache management operations using streaming engine

Storage organization for transposing a matrix using a streaming engine

Mechanism to queue multiple streams to run on streaming engine

TRAN JONATHAN SON HUNG

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

CHACHAD ABHIJEET ASHOK

Cache with multiple access pipelines

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

DAMODARAN RAGURAM

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence