Inventor

WONG SAU CHING

US53 patents

⚠️ This page may combine multiple inventors who share the name “WONG SAU CHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WONG SAU CHING

MULTI LEVEL MEMORY TECHNOLOGY

Parallel programming of multiple-bit-per-cell memory cells on a continuous word line

Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units

Multi-bit-cell non-volatile memory with maximized data capacity

Read and write operations using constant row line voltage and variable column line load

Flash memory array partitioning architectures

Data management for multi-bit-per-cell memories

Dynamic refresh that changes the physical storage locations of data in flash memory

Bit line reference circuits for binary and multiple-bit-per-cell memories

Contactless flash memory with buried diffusion bit/virtual ground lines

Flash memory with dynamic refresh

Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell

Refresh operations that change address mappings in a non-volatile memory

Bi-directional floating gate nonvolatile memory

Contactless flash memory with shared buried diffusion bit line architecture

Erasing storage nodes in a bi-directional nonvolatile memory cell

Accessing individual storage nodes in a bi-directional nonvolatile memory cell

Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data

SAMSUNG ELECTRONICS CO LTD

Programming of multi-level memory cells on a continuous word line

Non-uniform programming pulse width for writing of multi-bit-per-cell memories

Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage

Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage

Efficient redundancy system for flash memories with uniformly sized blocks

Periodic refresh operations for non-volatile multiple-bit-per-cell memory

Contactless bidirectional nonvolatile memory

Adaptive parallel writing to nonvolatile memory cells

Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage

Bit line reference circuits for binary and multiple-bit-per-cell memories

Programming nonvolatile memory cells through a series of predetermined threshold voltages

Programming nonvolatile memory cells through a series of predetermined threshold voltages

Programming nonvolatile memory cells through a series of predetermined threshold voltages

Programming nonvolatile memory cells through a series of predetermined threshold voltages

Fabricating bi-directional nonvolatile memory cells

ALTERA CORP

Programmable logic device with array blocks with programmable clocking

Programmable logic devices with spare circuits for use in replacing defective circuits

Programmable logic device with array blocks connected via programmable interconnect

Programmable logic array device using EPROM technology

Programmable logic array device using EPROM technology

Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits

Multifunction flip-flop-type circuit

Bit line sense amplifier for programmable logic devices

SANDISK CORP

Non-volatile content addressable memory

Data encoding for content addressable memories

Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories

Content addressable memory cell and array architectures having low transistor counts

WONG SAU CHING

Adaptive operations for nonvolatile memories

Parallel programming of nonvolatile memory cells

Reading a multi-bit value from a memory cell

(unassigned)

Memory with offset bank select cells at opposite ends of buried diffusion lines

Nonvolatile semiconductor memory device

INTEL CORP

Mos-ram