Inventor

GIRKAR MILIND B

US52 patents

⚠️ This page may combine multiple inventors who share the name “GIRKAR MILIND B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GIRKAR MILIND B

INTEL CORP

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for tile store

Systems, apparatuses, and methods for chained fused multiply add

Method and apparatus for exploiting thread-level parallelism

Systems, apparatuses, and methods for fused multiply add

Data element comparison processors, methods, systems, and instructions

Loop vectorization methods and apparatus

Systems, apparatuses, and methods for chained fused multiply add

Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality

Vector address conflict resolution with vector population count functionality

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Systems, apparatuses, and methods for fused multiply add

Loop vectorization methods and apparatus

Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register

Systems, apparatuses, and methods for chained fused multiply add

Method and apparatus for performing a vector permute with an index and an immediate

Systems, apparatuses, and methods for data speculation execution

Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register

Apparatus and method to obtain information regarding suppressed faults

Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hosting

Systems, apparatuses, and methods for addition of partial products

Systems, apparatuses, and methods for chained fused multiply add

Systems, apparatuses, and methods for addition of partial products

Systems, apparatuses, and methods for data speculation execution

Providing multiple memory modes for a processor including internal memory

Data element comparison processors, methods, systems, and instructions

Systems, apparatuses, and methods for data speculation execution

Systems, apparatuses, and methods for data speculation execution

Architectural register replacement for instructions that use multiple architectural registers

Systems, apparatuses, and methods for data speculation execution

Systems, apparatuses, and methods for data speculation execution

Vector store/load instructions for array of structures

Method and apparatus for performing conflict detection using vector comparison operations

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

Gathering and scattering multiple data elements

Fused multiply-add (FMA) low functional unit

Floating point (FP) add low instructions functional unit

Providing multiple memory modes for a processor including internal memory

Providing multiple memory modes for a processor including internal memory

HUGHES CHRISTOPHER J

Gathering and scattering multiple data elements

Vector conflict instructions

Gathering and scattering multiple data elements

HANKINS RICHARD A

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

OULD-AHMED-VALL ELMOUSTAPHA

Systems, apparatuses, and methods for data speculation execution