Inventor

MANDELMAN JACK A

US349 patents

⚠️ This page may combine multiple inventors who share the name “MANDELMAN JACK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANDELMAN JACK A

IBM

Stress inducing spacers

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device

Self-trimming method on looped patterns

Semiconductor device of an embedded DRAM on SOI substrate

Silicon-on-insulator vertical array device trench capacitor DRAM

SOI hybrid structure with selective epitaxial growth of silicon

Method for hybrid DRAM cell utilizing confined strap isolation

Structure for folded architecture pillar memory cell

Shared body and diffusion contact structure and method for fabricating same

Mixed memory integration with NVRAM, dram and sram cell structures on same substrate

Embedded DRAM on silicon-on-insulator substrate

Trench storage dynamic random access memory cell with vertical transfer device

Structure for folded architecture pillar memory cell

DRAM cell with grooved transfer device

Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications

Two-device memory cell on SOI for merged logic and memory applications

Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory

Tunneling effect transistor with self-aligned gate

Sub-lithographic local interconnects, and methods for forming same

Strained finFET CMOS device structures

Isolation structures for imposing stress patterns

Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby

Structure and method for MOSFET with metallic gate electrode

SOI hybrid structure with selective epitaxial growth of silicon

SIO stacked DRAM logic

SOI stacked DRAM logic

High-density dual-cell flash memory structure

Transistors having independently adjustable parameters

Method for novel SOI DRAM BICMOS NPN

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application

Structure and method for producing low leakage isolation devices

Method and apparatus for increasing interchip communications rates

Filling of high aspect ratio trench isolation

Power transistor having vertical FETs and method for making same

SOI/bulk hybrid substrate and method of forming the same

Methods to enhance SOI SRAM cell stability

High performance multi-mesa field effect transistor

SOI DRAM with field-shield isolation and body contact

Field effect transistor having a floating gate

DRAM cell having an annular signal transfer region

Field effect transistor having a floating gate

Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications

Vertical MOSFET SRAM cell

MOS transistor

Quantum conductive barrier for contact to shallow diffusion region

Reduction of polysilicon stress in trench capacitors

Word line driver for dynamic random access memories

Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch

INFINEON TECHNOLOGIES CORP

Single sided buried strap