Inventor
MIGNOT YANN
US106 patents
⚠️ This page may combine multiple inventors who share the name “MIGNOT YANN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
44 patentsUS10304744B1May 28, 2019
Inverse tone direct print EUV lithography enabled by selective material deposition
IBM23 citations94
US10020255B1Jul 10, 2018
Integration of super via structure in BEOL
IBM36 citations94
US10020254B1Jul 10, 2018
Integration of super via structure in BEOL
IBM39 citations94
US9373582B1Jun 21, 2016
Self aligned via in integrated circuit
IBM18 citations92
US10361129B1Jul 23, 2019
Self-aligned double patterning formed fincut
IBM14 citations86
US10658180B1May 19, 2020
EUV pattern transfer with ion implantation and reduced impact of resist residue
IBM6 citations84
US10622301B2Apr 14, 2020
Method of forming a straight via profile with precise critical dimension control
IBM8 citations84
US10276434B1Apr 30, 2019
Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
IBM6 citations84
US9390967B2Jul 12, 2016
Method for residue-free block pattern transfer onto metal interconnects for air gap formation
IBM9 citations84
US9385078B1Jul 5, 2016
Self aligned via in integrated circuit
IBM11 citations83
US12094774B2Sep 17, 2024
Back-end-of-line single damascene top via spacer defined by pillar mandrels
IBM2 citations73
US11600325B2Mar 7, 2023
Non volatile resistive memory logic device
IBM2 citations73
US11164778B2Nov 2, 2021
Barrier-free vertical interconnect structure
IBM3 citations73
US11101175B2Aug 24, 2021
Tall trenches for via chamferless and self forming barrier
IBM2 citations73
US11056426B2Jul 6, 2021
Metallization interconnect structure formation
IBM6 citations73
US11037822B2Jun 15, 2021
Svia using a single damascene interconnect
IBM2 citations73
US10937653B2Mar 2, 2021
Multiple patterning scheme integration with planarized cut patterning
IBM1 citations73
US10825726B2Nov 3, 2020
Metal spacer self aligned multi-patterning integration
IBM2 citations73
US10672705B2Jun 2, 2020
Method of forming a straight via profile with precise critical dimension control
IBM3 citations73
US10615027B1Apr 7, 2020
Stack viabar structures
IBM2 citations73
US10607922B1Mar 31, 2020
Controlling via critical dimension during fabrication of a semiconductor wafer
IBM3 citations73
US10475905B2Nov 12, 2019
Techniques for vertical FET gate length control
IBM4 citations73
US10361125B2Jul 23, 2019
Methods and structures for forming uniform fins when using hardmask patterns
IBM4 citations73
US9252051B1Feb 2, 2016
Method for top oxide rounding with protection of patterned features
IBM3 citations73
US12010930B2Jun 11, 2024
Wrap-around projection liner for AI device
IBM2 citations72
US9508560B1Nov 29, 2016
SiARC removal with plasma etch and fluorinated wet chemical solution combination
IBM4 citations72
US11239077B2Feb 1, 2022
Litho-etch-litho-etch with self-aligned blocks
IBM2 citations71
US11152298B2Oct 19, 2021
Metal via structure
IBM3 citations71
US10903111B2Jan 26, 2021
Semiconductor device with linerless contacts
IBM4 citations70
US12525529B2Jan 13, 2026
Forming line end vias
IBM0 citations63
US12400859B2Aug 26, 2025
Metal hard mask for precise tuning of mandrels
IBM0 citations63
US12369494B2Jul 22, 2025
MRAM top electrode structure with liner layer
IBM0 citations63
US12142562B2Nov 12, 2024
Subtractive metal etch with improved isolation for BEOL interconnect and cross point
IBM0 citations63
US11901440B2Feb 13, 2024
Sacrificial fin for self-aligned contact rail formation
IBM0 citations63
US11798842B2Oct 24, 2023
Line formation with cut-first tip definition
IBM0 citations63
US11646358B2May 9, 2023
Sacrificial fin for contact self-alignment
IBM0 citations63
US11316029B2Apr 26, 2022
Sacrificial fin for contact self-alignment
IBM0 citations63
US11171001B2Nov 9, 2021
Multiple patterning scheme integration with planarized cut patterning
IBM0 citations63
US11107727B2Aug 31, 2021
Double metal double patterning with vias extending into dielectric
IBM0 citations63
US11069564B2Jul 20, 2021
Double metal patterning
IBM0 citations63
US11031246B2Jun 8, 2021
EUV pattern transfer with ion implantation and reduced impact of resist residue
IBM0 citations63
US10985025B2Apr 20, 2021
Fin cut profile using fin base liner
IBM0 citations63
US10971356B2Apr 6, 2021
Stack viabar structures
IBM0 citations63
US10957552B2Mar 23, 2021
Extreme ultraviolet lithography patterning with directional deposition
IBM0 citations63
ST MICROELECTRONICS INC
5 patentsUS9679899B2Jun 13, 2017
Co-integration of tensile silicon and compressive silicon germanium
ST MICROELECTRONICS INC5 citations84
US9466563B2Oct 11, 2016
Interconnect structure for an integrated circuit and method of fabricating an interconnect structure
ST MICROELECTRONICS INC7 citations82
US10354927B2Jul 16, 2019
Co-integration of tensile silicon and compressive silicon germanium
ST MICROELECTRONICS INC1 citations73
US9214429B2Dec 15, 2015
Trench interconnect having reduced fringe capacitance
ST MICROELECTRONICS INC5 citations71
US11264286B2Mar 1, 2022
Co-integration of tensile silicon and compressive silicon germanium
ST MICROELECTRONICS INC0 citations63
GLOBALFOUNDRIES INC
1 patentShowing the top 50 of 106 patents by PatentIndex Score.