Inventor
STRONG VERONICA
US25 patents
⚠️ This page may combine multiple inventors who share the name “STRONG VERONICA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS11049791B1Jun 29, 2021
Heat spreading layer integrated within a composite IC die structure and methods of forming the same
INTEL CORP7 citations84
US11133263B2Sep 28, 2021
High-density interconnects for integrated circuit packages
INTEL CORP6 citations83
US11728258B2Aug 15, 2023
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
INTEL CORP2 citations73
US11257745B2Feb 22, 2022
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
INTEL CORP2 citations73
US10998272B2May 4, 2021
Organic interposers for integrated circuit packages
INTEL CORP2 citations72
US12400934B2Aug 26, 2025
Dielectric film coating for through glass vias and plane surface roughness mitigation
INTEL CORP1 citations64
US12598997B2Apr 7, 2026
Inductor with integrated magnetics
INTEL CORP0 citations62
US12573744B2Mar 10, 2026
Wideband antennas in glass through direct via feeding and glass stacking
INTEL CORP0 citations62
US12525496B2Jan 13, 2026
Glass vias and planes with reduced tapering
INTEL CORP0 citations62
US12444619B2Oct 14, 2025
Physical vapor deposition seeding for high aspect ratio vias in glass core technology
INTEL CORP0 citations62
US12424719B2Sep 23, 2025
Compact surface transmission line waveguides with vertical ground planes
INTEL CORP0 citations62
US12424716B2Sep 23, 2025
RF filters and multiplexers manufactured in the core of a package substrate using glass core technology
INTEL CORP0 citations62
US12368091B2Jul 22, 2025
Package substrate with glass core having vertical power planes for improved power delivery
INTEL CORP0 citations62
US12347761B2Jul 1, 2025
Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate
INTEL CORP0 citations62
US12205902B2Jan 21, 2025
High-density interconnects for integrated circuit packages
INTEL CORP0 citations62
US11694951B2Jul 4, 2023
Zero-misalignment two-via structures
INTEL CORP0 citations62
US11664303B2May 30, 2023
Interconnection structure fabrication using grayscale lithography
INTEL CORP0 citations62
US11581238B2Feb 14, 2023
Heat spreading layer integrated within a composite IC die structure and methods of forming the same
INTEL CORP0 citations62
US11222836B2Jan 11, 2022
Zero-misalignment two-via structures
INTEL CORP0 citations62
US11101205B2Aug 24, 2021
Interconnection structure fabrication using grayscale lithography
INTEL CORP0 citations62
US11502037B2Nov 15, 2022
Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating
INTEL CORP0 citations61
US11328996B2May 10, 2022
Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating
INTEL CORP0 citations61
US11460499B2Oct 4, 2022
Dual sided thermal management solutions for integrated circuit packages
INTEL CORP0 citations51