Inventor

VEGA REINALDO

US80 patents

⚠️ This page may combine multiple inventors who share the name “VEGA REINALDO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VEGA REINALDO

IBM

Vertical field effect transistors with metallic source/drain regions

Formation of air-gap spacer in transistor

Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts

Gate-all-around field effect transistor having multiple threshold voltages

Three-dimensional stacked junctionless channels for dense SRAM

FinFET having suppressed leakage current

Formation of metal resistor and e-fuse

Decoupling capacitor inside gate cut trench

Complementary FET (CFET) buried sidewall contact with spacer foot

Phase-change memory device with reduced programming voltage

Contact resistance reduction in nanosheet device structure

Intercalation cells for multi-task learning

Paired intercalation cells for drift migration

External resistance reduction with embedded bottom source/drain for vertical transport FET

Gate-all-around field effect transistor having multiple threshold voltages

Three-dimensional stacked junctionless channels for dense SRAM

Vertical field effect transistors with metallic source/drain regions

Nanosheet with dual isolation regions separated by buried inner spacer

Vertical-transport field-effect transistor with backside source/drain connections

Negative capacitance gate-all-around transistor with tunable capacitance ratio

VTFET circuit with optimized output

Reduced capacitance between power via bar and gates

Source/drain contact at tight cell boundary

Wrap around metal via structure

Vertical transport field effect transistor (VTFET) with backside wraparound contact

Pass-through wiring in notched interconnect

Vertical-transport field-effect transistor with backside gate contact

Phase change memory cell with superlattice based thermal barrier

Random weight initialization of non-volatile memory array

Buried local interconnect between complementary field-effect transistor cells

Ferroelectric and paraelectric stack capacitors

Gate contact inside gate cut trench

Full nanosheet airgap spacer

CBRAM with controlled bridge location

Resistive memory with embedded metal oxide fin for gradual switching

Field effect transistor (FET) devices

Resistive switching memory cell

Resistive switching memory cell

NCFETS with complimentary capacitance matching using stacked n-type and p-type nanosheets

Vertical resistive memory device with embedded selectors

Reducing parasitic capacitance within semiconductor devices

Tapered resistive memory with interface dipoles

Resistive memory with embedded metal oxide fin for gradual switching

Vertical intercalation device for neuromorphic computing

Resistive memory with core and shell oxides and interface dipoles

CBRAM with controlled bridge location

Backside self aligned skip via

GLOBALFOUNDRIES INC

Anisotropic dielectric material gate spacer for a field effect transistor

Methods of forming uniform and pitch independent fin recess

ALPTEKIN EMRE

Contact structures for semiconductor transistors