Inventor

LEMAY RICHARD A

US45 patents

⚠️ This page may combine multiple inventors who share the name “LEMAY RICHARD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEMAY RICHARD A

HONEYWELL INF SYSTEMS

Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus

Control system providing for the transfer of data in a communications processing system employing channel dedicated control blocks

Data processing system providing split bus cycle operation

Apparatus for processing data transfer requests in a data processing system

Memory management unit for developing multiple physical addresses in parallel for use in a cache memory

Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories

Hardware/firmware communication line adapter

Multiple length address formation in a microprogrammed data processing system

System providing multiple outstanding information requests

System providing multiple fetch bus cycle operation

Communications processor employing line-dedicated memory tables for supervising data transfers

Address boundary detector

Instruction decoding logic system

Logic control system including cache memory for CPU-memory transfers

Logic control system for efficient memory to CPU transfers

Bus sourcing and shifter control of a central processing unit

Apparatus for performing the scientific add instruction

System providing adaptive response in information requesting unit

Transfer control technique between two units included in a data processing system

Two stage selection based on time of arrival and predetermined priority in a bus priority resolver

Flexible logic transfer and instruction decoding system

Logic transfer and decoding system

Buffer system for supply procedure words to a central processor unit

Automatic operand length control of the result of a scientific arithmetic operation

Hardware demand fetch cycle system interface

BULL HN INFORMATION SYST

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

Storage of input/output command timeout and acknowledge responses

Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units

Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories

High performance burst read data transfer operation

Executing programs of a first system on a second system

Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols

Programmable system bus priority network

Processor bus access

Microprocessor bus interface protocol analyzer

State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections

Microprocessor vectored interrupts

Memory addressing arrangement

Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank

Data selection matrix

Power-on sequencing apparatus for initializing and testing a system processing unit

Buffered address stack register with parallel input registers and overflow protection

HONEYWELL BULL

Multifunction arithmetic indicator

Time partitioned bus arrangement

HUTTON PRC TECHNOLOGY PARTNERS

Memory failure detection apparatus