Inventor
INGLE AJAY ANANT
US31 patents
⚠️ This page may combine multiple inventors who share the name “INGLE AJAY ANANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
10 patentsUS7620778B2Nov 17, 2009
Low power microprocessor cache memory and method of operation
QUALCOMM INC5 citations62
US7505342B2Mar 17, 2009
Memory bus output driver of a multi-bank memory device and method therefor
QUALCOMM INC4 citations61
US8943293B2Jan 27, 2015
Configurable cache and method to configure same
QUALCOMM INC0 citations52
US8812789B2Aug 19, 2014
Systems and methods for cache line replacement
QUALCOMM INC0 citations52
US9639356B2May 2, 2017
Arbitrary size table lookup and permutes with crossbar
QUALCOMM INC0 citations50
US9130786B2Sep 8, 2015
Device and method for computing a channel estimate
QUALCOMM INC0 citations50
US9639503B2May 2, 2017
Vector indirect element vertical addressing mode with horizontal permute
QUALCOMM INC1 citations49
US10489155B2Nov 26, 2019
Mixed-width SIMD operations using even/odd register pairs for wide data elements
QUALCOMM INC0 citations40
US9268571B2Feb 23, 2016
Selective coupling of an address line to an element bank of a vector register file
QUALCOMM INC0 citations39
US10466967B2Nov 5, 2019
System and method for piecewise linear approximation
QUALCOMM INC0 citations37
INGLE AJAY ANANT
6 patentsUS8812516B2Aug 19, 2014
Determining top N or bottom N data values and positions
INGLE AJAY ANANT7 citations82
US9239799B2Jan 19, 2016
Memory management unit directed access to system interfaces
INGLE AJAY ANANT4 citations71
US8429378B2Apr 23, 2013
System and method to manage a translation lookaside buffer
INGLE AJAY ANANT4 citations56
US8868888B2Oct 21, 2014
System and method of executing instructions in a multi-stage data processing pipeline
INGLE AJAY ANANT1 citations51
US8464000B2Jun 11, 2013
Systems and methods for cache line replacements
INGLE AJAY ANANT1 citations51
US8185721B2May 22, 2012
Dual function adder for computing a hardware prefetch address and an arithmetic operation value
INGLE AJAY ANANT0 citations51
KOOB CHRISTOPHER EDWARD
3 patentsUS8266409B2Sep 11, 2012
Configurable cache and method to configure same
KOOB CHRISTOPHER EDWARD5 citations73
US8719503B2May 6, 2014
Configurable cache and method to configure same
KOOB CHRISTOPHER EDWARD4 citations72
US9824013B2Nov 21, 2017
Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors
KOOB CHRISTOPHER EDWARD0 citations40
CODRESCU LUCIAN
3 patentsUS8990543B2Mar 24, 2015
System and method for generating and using predicates within a single instruction packet
CODRESCU LUCIAN3 citations61
US8260990B2Sep 4, 2012
Selective preclusion of a bus access request
CODRESCU LUCIAN0 citations51
US9678754B2Jun 13, 2017
System and method of processing hierarchical very long instruction packets
CODRESCU LUCIAN0 citations40