Inventor

HORST ROBERT W

US87 patents

⚠️ This page may combine multiple inventors who share the name “HORST ROBERT W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HORST ROBERT W

TANDEM COMPUTERS INC

Encoding for communicating data and commands

Logical, fail-functional, dual central processor units formed from three processor units

Method and apparatus for synchronizing a plurality of processors

Multiple-processor computer system with asynchronous execution of identical code streams

Memory system using linear array wafer scale integration architecture

Network message routing using routing table information and supplemental enable information for deadlock prevention

Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source

Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions

Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Routing arbitration for shared resources

Task flow computer architecture

Method and apparatus for executing tasks by following a linked list of memory packets

Method and apparatus for synchronizing a plurality of processors

Method and apparatus for synchronizing a plurality of processors

Method for verifying responses to messages using a barrier message

Refresh control for dynamic memory in multiple processor system

Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel

Interrupts between asynchronously operating CPUs in fault tolerant computer system

Refresh control for dynamic memory in multiple processor system

Computer architecture capable of concurrent issuance and execution of general purpose multiple instruction

Microinstruction sequencer having multiple control stores for loading different rank registers in parallel

Latency reduction and routing arbitration for network message routers

TIBION CORP

Active muscle assistance and resistance device and method

Active muscle assistance device and method

Method and devices for moving a body joint

Electrostatic actuator with fault tolerant electrode structure

Rotary actuator

High-torque motor

3WARE INC

Methods and systems for selecting block sizes for use with disk arrays

Use of activity bins to increase the performance of disk arrays

Use of deferred write completion interrupts to increase the performance of disk operations

Methods and systems for dynamically distributing disk array data accesses

Spatial display of disk drive activity data

HORST ROBERT W

Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement

Intention-based therapy device and method

Actuator system with a multi-motor assembly for extending and flexing a joint

Foot pad device and method of obtaining weight data

Actuator system and method for extending a joint

HEWLETT PACKARD DEVELOPMENT CO

System and method for configuring adaptive sets of links between routers in a system area network (SAN)

Parallel pipelined merge engines

Method and apparatus for cluster interconnection using multi-port nodes and multiple routing fabrics

Network topology with asymmetric fabrics

COMPAQ COMPUTER CORP

Multiple processor system with standby sparing

Self-checked, lock step processor pairs

3WARE

Pluggable drive carrier assembly

Disk drive data protection using clusters containing error detection sectors

APPLIED MICRO CIRCUITS CORP

Use of activity bins to increase the performance of disk arrays

TANDEM COMP INC

Method of data communication flow control in a data processing system using busy/ready commands

ALTERG INC

Therapeutic method and device for rehabilitation