P

Inventor

ROUSSEL PATRICE

US32 patents
⚠️ This page may combine multiple inventors who share the name “ROUSSEL PATRICE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

28 patents
US6425073B2Jul 23, 2002

Method and apparatus for staggering execution of an instruction

INTEL CORP85 citations98
US6418529B1Jul 9, 2002

Apparatus and method for performing intra-add operation

INTEL CORP107 citations98
US5995122ANov 30, 1999

Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format

INTEL CORP112 citations98
US6292815B1Sep 18, 2001

Data conversion between floating point packed format and integer scalar format

INTEL CORP98 citations97
US7853778B2Dec 14, 2010

Load/move and duplicate instructions for a processor

INTEL CORP35 citations96
US6502115B2Dec 31, 2002

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

INTEL CORP50 citations96
US6266769B1Jul 24, 2001

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

INTEL CORP49 citations96
US6263426B1Jul 17, 2001

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

INTEL CORP55 citations96
US6247116B1Jun 12, 2001

Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

INTEL CORP69 citations96
US6925553B2Aug 2, 2005

Staggering execution of a single packed data instruction using the same circuit

INTEL CORP30 citations95
US6230257B1May 8, 2001

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

INTEL CORP39 citations95
US6230253B1May 8, 2001

Executing partial-width packed data instructions

INTEL CORP65 citations95
US6122725ASep 19, 2000

Executing partial-width packed data instructions

INTEL CORP65 citations95
US6041404AMar 21, 2000

Dual function system and method for shuffling packed data elements

INTEL CORP162 citations95
US6317824B1Nov 13, 2001

Method and apparatus for performing integer operations in response to a result of a floating point operation

INTEL CORP85 citations94
US7366881B2Apr 29, 2008

Method and apparatus for staggering execution of an instruction

INTEL CORP11 citations92
US6961845B2Nov 1, 2005

System to perform horizontal additions

INTEL CORP17 citations92
US6721866B2Apr 13, 2004

Unaligned memory operands

INTEL CORP37 citations92
US6480868B2Nov 12, 2002

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

INTEL CORP37 citations92
US7216138B2May 8, 2007

Method and apparatus for floating point operations and format conversion operations

INTEL CORP40 citations91
US7395302B2Jul 1, 2008

Method and apparatus for performing horizontal addition and subtraction

INTEL CORP11 citations84
US6970994B2Nov 29, 2005

Executing partial-width packed data instructions

INTEL CORP12 citations84
US7467286B2Dec 16, 2008

Executing partial-width packed data instructions

INTEL CORP8 citations74
US6687810B2Feb 3, 2004

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

INTEL CORP5 citations73
US8032735B2Oct 4, 2011

Load/move duplicate instructions for a processor

INTEL CORP2 citations63
US6694426B2Feb 17, 2004

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

INTEL CORP2 citations62
US9043583B2May 26, 2015

Load/move and duplicate instructions for a processor

INTEL CORP0 citations52
US7392275B2Jun 24, 2008

Method and apparatus for performing efficient transformations with horizontal addition and subtraction

INTEL CORP1 citations51

ROUSSEL PATRICE

4 patents