Inventor
DALLA LIBERA GIOVANNA
IT18 patents
⚠️ This page may combine multiple inventors who share the name “DALLA LIBERA GIOVANNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS SRL
13 patentsUS6624015B2Sep 23, 2003
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions
ST MICROELECTRONICS SRL17 citations92
US6268247B1Jul 31, 2001
Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method
ST MICROELECTRONICS SRL26 citations92
US6573130B1Jun 3, 2003
Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors
ST MICROELECTRONICS SRL17 citations84
US6548857B2Apr 15, 2003
Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process
ST MICROELECTRONICS SRL13 citations84
US6576517B1Jun 10, 2003
Method for obtaining a multi-level ROM in an EEPROM process flow
ST MICROELECTRONICS SRL8 citations73
US6521957B2Feb 18, 2003
Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
ST MICROELECTRONICS SRL10 citations73
US6479347B1Nov 12, 2002
Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells
ST MICROELECTRONICS SRL12 citations73
US6194270B1Feb 27, 2001
Process for the manufacturing of an electrically programmable non-volatile memory device
ST MICROELECTRONICS SRL12 citations73
US6204531B1Mar 20, 2001
Non-volatile memory structure and corresponding manufacturing process
ST MICROELECTRONICS SRL2 citations63
US6300181B1Oct 9, 2001
Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors
ST MICROELECTRONICS SRL5 citations62
US6284607B1Sep 4, 2001
Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide
ST MICROELECTRONICS SRL3 citations62
US6177313B1Jan 23, 2001
Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
ST MICROELECTRONICS SRL4 citations62
US6444526B1Sep 3, 2002
Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells
ST MICROELECTRONICS SRL0 citations41
SGS THOMSON MICROELECTRONICS
5 patentsUS6432762B1Aug 13, 2002
Memory cell for EEPROM devices, and corresponding fabricating process
SGS THOMSON MICROELECTRONICS9 citations73
US5985718ANov 16, 1999
Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type
SGS THOMSON MICROELECTRONICS12 citations73
US6320219B1Nov 20, 2001
Memory cell for EEPROM devices and corresponding fabricating process
SGS THOMSON MICROELECTRONICS2 citations62
US6097057AAug 1, 2000
Memory cell for EEPROM devices, and corresponding fabricating process
SGS THOMSON MICROELECTRONICS2 citations62
US6080626AJun 27, 2000
Memory cell for EEPROM devices, and corresponding fabricating process
SGS THOMSON MICROELECTRONICS1 citations51