Inventor
GALBIATI NADIA
IT15 patents
Patents
15 patentsUS6624015B2Sep 23, 2003
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions
ST MICROELECTRONICS SRL17 citations92
US6351008B1Feb 26, 2002
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions
ST MICROELECTRONICS SRL17 citations92
US6281077B1Aug 28, 2001
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions
ST MICROELECTRONICS SRL27 citations92
US6251728B1Jun 26, 2001
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions
ST MICROELECTRONICS SRL17 citations92
US6573130B1Jun 3, 2003
Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors
ST MICROELECTRONICS SRL17 citations84
US6576517B1Jun 10, 2003
Method for obtaining a multi-level ROM in an EEPROM process flow
ST MICROELECTRONICS SRL8 citations73
US6521957B2Feb 18, 2003
Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
ST MICROELECTRONICS SRL10 citations73
US6420769B2Jul 16, 2002
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions
ST MICROELECTRONICS SRL13 citations73
US6274411B1Aug 14, 2001
Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks
ST MICROELECTRONICS SRL14 citations73
US6414349B1Jul 2, 2002
High efficiency memory device
ST MICROELECTRONICS SRL2 citations62
US6396101B2May 28, 2002
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions
ST MICROELECTRONICS SRL2 citations62
US6300181B1Oct 9, 2001
Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors
ST MICROELECTRONICS SRL5 citations62
US6284607B1Sep 4, 2001
Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide
ST MICROELECTRONICS SRL3 citations62
US6177313B1Jan 23, 2001
Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
ST MICROELECTRONICS SRL4 citations62
US6444526B1Sep 3, 2002
Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells
ST MICROELECTRONICS SRL0 citations41