Inventor

NARAYANAN SRIDHAR

US26 patents

⚠️ This page may combine multiple inventors who share the name “NARAYANAN SRIDHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYANAN SRIDHAR

SUN MICROSYSTEMS INC

Flip-flop design and technique for scan chain diagnosis

Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits

Mutual exclusivity circuit for use in test pattern application scan architecture circuits

Pipelined scan enable for fast scan testing

Apparatus and method for high speed shifting of test data through an integrated circuit

Automated scan insertion flow for control block design

Circuit for avoiding contention in one-hot or one-cold multiplexer designs

Method for ensuring mutual exclusivity of selected signals during application of test patterns

Method for operating a boundary scan cell design for high performance I/O cells

Method and apparatus for scan test of SRAM for microprocessors without full scan capability

Boundary scan cell design for high performance I/O cells

Method for debugging an integrated circuit

Spatial and temporal alignment of a scan dump for debug of scan-based designs

CUMMINS GENERATOR TECHNOLOGIES

Generator

Generator

Generator

Generator

Terminal board

MANOVIT CHAIYASIT

Method and system for verifying power-optimized electronic designs using equivalency checking

Method for clock gating circuits

Method and apparatus for verifying output-based clock gating

NARAYANAN SRIDHAR

Reducing power consumption in a segmented memory

Reducing dynamic power consumption of a memory circuit

CAMPBELL BRIAN J

Clock gater with test features and low setup time

APPLE INC

Clock gater with test features and low setup time

XILINX INC

Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis