Inventor

SO BYUNG-SE

KR43 patents

Patents

43 patents

US7215561B2May 8, 2007

Semiconductor memory system having multiple system data buses

SAMSUNG ELECTRONICS CO LTD90 citations97

US6414904B2Jul 2, 2002

Two channel memory system having shared control and address bus and memory modules used therefor

SAMSUNG ELECTRONICS CO LTD85 citations97

US6480409B2Nov 12, 2002

Memory modules having integral terminating resistors and computer system boards for use with same

SAMSUNG ELECTRONICS CO LTD52 citations95

US7313715B2Dec 25, 2007

Memory system having stub bus configuration

SAMSUNG ELECTRONICS CO LTD31 citations93

US7818488B2Oct 19, 2010

Memory module with registers

SAMSUNG ELECTRONICS CO LTD24 citations92

US7276786B2Oct 2, 2007

Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted

SAMSUNG ELECTRONICS CO LTD32 citations92

US7180327B2Feb 20, 2007

Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode

SAMSUNG ELECTRONICS CO LTD27 citations92

US6836138B1Dec 28, 2004

Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same

SAMSUNG ELECTRONICS CO LTD24 citations92

US6815621B2Nov 9, 2004

Chip scale package, printed circuit board, and method of designing a printed circuit board

SAMSUNG ELECTRONICS CO LTD36 citations92

US6772262B1Aug 3, 2004

Memory module with improved data bus performance

SAMSUNG ELECTRONICS CO LTD19 citations92

US6252805B1Jun 26, 2001

Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode

SAMSUNG ELECTRONICS CO LTD22 citations92

US7615869B2Nov 10, 2009

Memory module with stacked semiconductor devices

SAMSUNG ELECTRONICS CO LTD20 citations91

US6382986B1May 7, 2002

Socket for mounting memory module boards on a printed circuit board

SAMSUNG ELECTRONICS CO LTD31 citations90

US7505521B2Mar 17, 2009

Data transmission system and method

SAMSUNG ELECTRONICS CO LTD8 citations84

US7656181B2Feb 2, 2010

Apparatus and method for testing circuit characteristics by using eye mask

SAMSUNG ELECTRONICS CO LTD11 citations81

US7566958B2Jul 28, 2009

Multi-chip package for reducing parasitic load of pin

SAMSUNG ELECTRONICS CO LTD6 citations74

US7447954B2Nov 4, 2008

Method of testing a memory module and hub of the memory module

SAMSUNG ELECTRONICS CO LTD8 citations73

US6828819B2Dec 7, 2004

High-speed memory system

SAMSUNG ELECTRONICS CO LTD11 citations73

US6632705B1Oct 14, 2003

Memory modules and packages using different orientations and terminal assignments

SAMSUNG ELECTRONICS CO LTD7 citations73

US5856982AJan 5, 1999

High-speed disturb testing method and word line decoder in semiconductor memory device

SAMSUNG ELECTRONICS CO LTD8 citations71

US7227258B2Jun 5, 2007

Mounting structure in integrated circuit module

SAMSUNG ELECTRONICS CO LTD8 citations68

US6587976B1Jul 1, 2003

Semiconductor device tester for measuring skew between output pins of a semiconductor device

SAMSUNG ELECTRONICS CO LTD9 citations66

US7847383B2Dec 7, 2010

Multi-chip package for reducing parasitic load of pin

SAMSUNG ELECTRONICS CO LTD3 citations63

US8051343B2Nov 1, 2011

Method of testing a memory module and hub of the memory module

SAMSUNG ELECTRONICS CO LTD2 citations62

US7849373B2Dec 7, 2010

Method of testing a memory module and hub of the memory module

SAMSUNG ELECTRONICS CO LTD2 citations62

US7539910B2May 26, 2009

Memory module test system for memory module including hub

SAMSUNG ELECTRONICS CO LTD4 citations62

US7334137B2Feb 19, 2008

Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller

SAMSUNG ELECTRONICS CO LTD2 citations62

US7254675B2Aug 7, 2007

Memory system having memory modules with different memory device loads

SAMSUNG ELECTRONICS CO LTD6 citations62

US6754112B2Jun 22, 2004

Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices

SAMSUNG ELECTRONICS CO LTD6 citations62

US7106613B2Sep 12, 2006

Memory module and a method of arranging a signal line of the same

SAMSUNG ELECTRONICS CO LTD2 citations61

US6714595B1Mar 30, 2004

Signal transmission circuits that use multiple input signals to generate a respective transmit signal and methods of operating the same

SAMSUNG ELECTRONICS CO LTD5 citations61

US7606110B2Oct 20, 2009

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

SAMSUNG ELECTRONICS CO LTD5 citations60

US10313217B2Jun 4, 2019

System on chip (SoC) capable of sharing resources with network device and devices having the SoC

SAMSUNG ELECTRONICS CO LTD0 citations52

US7868438B2Jan 11, 2011

Multi-chip package for reducing parasitic load of pin

SAMSUNG ELECTRONICS CO LTD0 citations52

US7350120B2Mar 25, 2008

Buffered memory module and method for testing same

SAMSUNG ELECTRONICS CO LTD0 citations52

US6870742B2Mar 22, 2005

System board

SAMSUNG ELECTRONICS CO LTD0 citations52

US7049849B2May 23, 2006

Signal transmission circuits that use multiple input signals to generate a respective transmit signal

SAMSUNG ELECTRONICS CO LTD0 citations51

US6990543B2Jan 24, 2006

Memory module with improved data bus performance

SAMSUNG ELECTRONICS CO LTD1 citations51

US7219274B2May 15, 2007

Memory module and method of testing the same

SAMSUNG ELECTRONICS CO LTD0 citations42

US7930465B2Apr 19, 2011

Determining operation mode for semiconductor memory device

SAMSUNG ELECTRONICS CO LTD0 citations41

SO BYUNG-SE

Patents

Semiconductor memory system having multiple system data buses

Two channel memory system having shared control and address bus and memory modules used therefor

Memory modules having integral terminating resistors and computer system boards for use with same

Memory system having stub bus configuration

Memory module with registers

Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted

Memory module system with efficient control of on-die termination

Multi-chip package for reducing parasitic load of pin

Memory module

Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode

Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same

Chip scale package, printed circuit board, and method of designing a printed circuit board

Memory module with improved data bus performance

Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode

Memory module with stacked semiconductor devices

Socket for mounting memory module boards on a printed circuit board

Data transmission system and method

Apparatus and method for testing circuit characteristics by using eye mask

Multi-chip package for reducing parasitic load of pin

Method of testing a memory module and hub of the memory module

High-speed memory system

Memory modules and packages using different orientations and terminal assignments

High-speed disturb testing method and word line decoder in semiconductor memory device

Mounting structure in integrated circuit module

Semiconductor device tester for measuring skew between output pins of a semiconductor device

Multi-chip package for reducing parasitic load of pin

Method of testing a memory module and hub of the memory module

Method of testing a memory module and hub of the memory module

Memory module test system for memory module including hub

Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller

Memory system having memory modules with different memory device loads

Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices

Memory module and a method of arranging a signal line of the same

Signal transmission circuits that use multiple input signals to generate a respective transmit signal and methods of operating the same

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

System on chip (SoC) capable of sharing resources with network device and devices having the SoC

Multi-chip package for reducing parasitic load of pin

Buffered memory module and method for testing same

System board

Signal transmission circuits that use multiple input signals to generate a respective transmit signal

Memory module with improved data bus performance

Memory module and method of testing the same

Determining operation mode for semiconductor memory device