Inventor
KIANIAN SOHRAB
US18 patents
Patents
18 patentsUS7307308B2Dec 11, 2007
Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation
SILICON STORAGE TECH INC61 citations98
US7533063B2May 12, 2009
Smart memory card wallet
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US6952034B2Oct 4, 2005
Semiconductor memory array of floating gate memory cells with buried source line and floating gate
SILICON STORAGE TECH INC64 citations96
US7190018B2Mar 13, 2007
Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation
SILICON STORAGE TECH INC22 citations92
US7074672B2Jul 11, 2006
Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
SILICON STORAGE TECH INC23 citations92
US6952033B2Oct 4, 2005
Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
SILICON STORAGE TECH INC17 citations92
US6891220B2May 10, 2005
Method of programming electrons onto a floating gate of a non-volatile memory cell
SILICON STORAGE TECH INC30 citations92
US6861315B1Mar 1, 2005
Method of manufacturing an array of bi-directional nonvolatile memory cells
SILICON STORAGE TECH INC31 citations92
US7411246B2Aug 12, 2008
Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
SILICON STORAGE TECH INC9 citations84
US7326614B2Feb 5, 2008
Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
SILICON STORAGE TECH INC15 citations84
US6917069B2Jul 12, 2005
Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
SILICON STORAGE TECH INC14 citations84
US7129536B2Oct 31, 2006
Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
SILICON STORAGE TECH INC7 citations74
US6940125B2Sep 6, 2005
Vertical NROM and methods for making thereof
SILICON STORAGE TECH INC11 citations74
US5852577ADec 22, 1998
Electrically erasable and programmable read-only memory having a small unit for program and erase
SILICON STORAGE TECH INC7 citations74
US7547603B2Jun 16, 2009
Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
SILICON STORAGE TECH INC2 citations63
US7144778B2Dec 5, 2006
Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
SILICON STORAGE TECH INC4 citations63
US7537996B2May 26, 2009
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate
SILICON STORAGE TECH INC2 citations62
US7205198B2Apr 17, 2007
Method of making a bi-directional read/program non-volatile floating gate memory cell
SILICON STORAGE TECH INC0 citations51