Inventor
HU YAW WEN
US26 patents
⚠️ This page may combine multiple inventors who share the name “HU YAW WEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILICON STORAGE TECH INC
13 patentsUS7868375B2Jan 11, 2011
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
SILICON STORAGE TECH INC230 citations98
US7927994B1Apr 19, 2011
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
SILICON STORAGE TECH INC73 citations97
US6952034B2Oct 4, 2005
Semiconductor memory array of floating gate memory cells with buried source line and floating gate
SILICON STORAGE TECH INC64 citations96
US6891220B2May 10, 2005
Method of programming electrons onto a floating gate of a non-volatile memory cell
SILICON STORAGE TECH INC30 citations92
US6429075B2Aug 6, 2002
Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby
SILICON STORAGE TECH INC19 citations92
US7668013B2Feb 23, 2010
Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio
SILICON STORAGE TECH INC17 citations91
US7129536B2Oct 31, 2006
Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
SILICON STORAGE TECH INC7 citations74
US7119396B2Oct 10, 2006
NROM device
SILICON STORAGE TECH INC7 citations74
US6369420B1Apr 9, 2002
Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby
SILICON STORAGE TECH INC10 citations74
US7547603B2Jun 16, 2009
Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
SILICON STORAGE TECH INC2 citations63
US6822287B1Nov 23, 2004
Array of integrated circuit units with strapping lines to prevent punch through
SILICON STORAGE TECH INC3 citations63
US7537996B2May 26, 2009
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate
SILICON STORAGE TECH INC2 citations62
US7974136B2Jul 5, 2011
Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio
SILICON STORAGE TECH INC2 citations61
INOTERA MEMORIES INC
9 patentsUS9171847B1Oct 27, 2015
Semiconductor structure
INOTERA MEMORIES INC11 citations84
US9018733B1Apr 28, 2015
Capacitor, storage node of the capacitor, and method of forming the same
INOTERA MEMORIES INC15 citations84
US9070782B2Jun 30, 2015
Semiconductor structure
INOTERA MEMORIES INC2 citations61
US9230967B2Jan 5, 2016
Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
INOTERA MEMORIES INC1 citations52
US9184166B2Nov 10, 2015
Manufacturing method of capacitor structure and semiconductor device using the same
INOTERA MEMORIES INC1 citations51
US9070740B2Jun 30, 2015
Memory unit, memory unit array and method of manufacturing the same
INOTERA MEMORIES INC0 citations40
US9035366B2May 19, 2015
Semiconductor device and manufacturing method therefor
INOTERA MEMORIES INC0 citations40
US8828843B2Sep 9, 2014
Method of manufacturing isolation structure
INOTERA MEMORIES INC0 citations39
US9496358B2Nov 15, 2016
Semiconductor device and fabrication method therefor
INOTERA MEMORIES INC0 citations34