Inventor

VENKATRAMAN RAMNATH

US34 patents

⚠️ This page may combine multiple inventors who share the name “VENKATRAMAN RAMNATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENKATRAMAN RAMNATH

LSI LOGIC CORP

Integrated circuit cell architecture configurable for memory or logic elements

Memory cell architecture for reduced routing congestion

Memory cell architecture

Fuse construction for integrated circuit structure having low dielectric constant dielectric material

Circuit for verifying the write speed of SRAM cells

Fuse construction for integrated circuit structure having low dielectric constant dielectric material

Method of forming metal fuses in CMOS processes with copper interconnect

Single channel four transistor SRAM

Ternary CAM bitcells

Method of forming metal fuses in CMOS processes with copper interconnect

Design and use of a spacer cell to support reconfigurable memories

Reconfigurable memory arrays

Optical proximity correction method using weighted priorities

MOTOROLA INC

Copper interconnect structure and method of formation

Method for forming a semiconductor device

Method of forming an interconnect structure

Method of alloying an interconnect structure with copper

Method of forming semiconductor device including interconnect barrier layers

Semiconductor device with a copper barrier layer and formation thereof

Process for fabricating a multilevel interconnect

Process for fabricating a metallized interconnect

LSI CORP

Basic cell architecture for structured application-specific integrated circuits

Modular design of multiport memory bitcells

Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas

Closed-loop adaptive voltage scaling for integrated circuits

SRAM based one-time-programmable memory

VENKATRAMAN RAMNATH

Integrated circuit cell architecture configurable for memory or logic elements

Basic cell architecture for structured ASICs

Power controller for SoC power gating applications

Defectivity-immune technique of implementing MIM-based decoupling capacitors

Basic cell architecture for structured application-specific integrated circuits

MBOUOMBOUO BENJAMIN

Optimization with adaptive body biasing

Total power optimization for a logic integrated circuit

WEIR BONNIE E

Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank