Inventor
ESPASA ROGER
ES17 patents
⚠️ This page may combine multiple inventors who share the name “ESPASA ROGER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS7627735B2Dec 1, 2009
Implementing vector memory operations
INTEL CORP45 citations94
US9785433B2Oct 10, 2017
Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding
INTEL CORP10 citations79
US10445244B2Oct 15, 2019
Method, system, and apparatus for page sizing extension
INTEL CORP1 citations71
US9654143B2May 16, 2017
Consecutive bit error detection and correction
INTEL CORP4 citations71
US10445092B2Oct 15, 2019
Method and apparatus for performing a vector permute with an index and an immediate
INTEL CORP3 citations69
US9934155B2Apr 3, 2018
Method, system, and apparatus for page sizing extension
INTEL CORP1 citations61
US10445245B2Oct 15, 2019
Method, system, and apparatus for page sizing extension
INTEL CORP0 citations51
US10296489B2May 21, 2019
Method and apparatus for performing a vector bit shuffle
INTEL CORP0 citations40
US10296334B2May 21, 2019
Method and apparatus for performing a vector bit gather
INTEL CORP0 citations40
US10713044B2Jul 14, 2020
Bit shuffle processors, methods, systems, and instructions
INTEL CORP0 citations36