Inventor

RESTAINO DARRYL D

US30 patents

⚠️ This page may combine multiple inventors who share the name “RESTAINO DARRYL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RESTAINO DARRYL D

IBM

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof

Diffusion barrier layer and semiconductor device containing same

Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof

Radio-frequency coil for use in an ionized physical vapor deposition apparatus

Wafer clamp ring for use in an ionized physical vapor deposition apparatus

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices

Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same

Advanced low dielectric constant organosilicon plasma chemical vapor deposition films

Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill

Method and apparatus to improve coating quality

Film planarization for low-k polymers used in semiconductor structures

Advanced low dielectric constant organosilicon plasma chemical vapor deposition films

Manufacturable CoWP metal cap process for copper interconnects

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

Laminated diffusion barrier

Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same

BEOL interconnect structures with improved resistance to stress

Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength

Metal deposition process for metal lines over topography

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

Void-free damascene copper deposition process and means of monitoring thereof

Manufacturable CoWP metal cap process for copper interconnects

Method for preventing backside defects in dielectric layers formed on semiconductor substrates

Method for reworking low-k polymers used in semiconductor structures

SAMSUNG ELECTRONICS CO LTD

Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby

Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses

SONY CORP

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

HOFFMAN JR WILLIAM K

Metrology management