Inventor

KIM BYEONG Y

US48 patents

⚠️ This page may combine multiple inventors who share the name “KIM BYEONG Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM BYEONG Y

IBM

Registration mark formation during sidewall image transfer process

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain

Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same

Capacitor trench-top dielectric for self-aligned device isolation

Metallized conductive strap spacer for SOI deep trench capacitor

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain

Pedestal collar structure for higher charge retention time in trench-type DRAM cells

Method of filling isolation trenches in a substrate

Wafer stress control and topography compensation

Multi-height multi-composition semiconductor fins

Registration mark formation during sidewall image transfer process

Shallow trench isolation structure compatible with SOI embedded DRAM

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

Poly filled substrate contact on SOI structure

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

Subground rule STI fill for hot structure

Shallow trench isolation structure having a nitride plug

Wet bottling process for small diameter deep trench capacitors

Embedded DRAM memory cell with additional patterning layer for improved strap formation

Method of forming an SOI substrate contact

Semiconductor substrate with multiple crystallographic orientations

Poly filled substrate contact on SOI structure

Registration mark formation during sidewall image transfer process

Structure and method to prevent EPI short between trenches in FinFET eDRAM

Registration mark formation during sidewall image transfer process

Structure and method to prevent EPI short between trenches in FINFET eDRAM

High density memory cells using lateral epitaxy

Method of making a semiconductor structure

Multiple crystallographic orientation semiconductor structures

Multiple crystallographic orientation semiconductor structures

KIM BYEONG Y

Shallow trench isolation structure having a nitride plug

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

Thermal dual gate oxide device integration

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

GLOBALFOUNDRIES INC

Fabrication of a deep trench memory cell

Self-aligned laterally extended strap for a dynamic random access memory cell

Capacitor-transistor strap connections for a memory cell

Integrated circuit structure with insulated memory device and related methods

CHENG KANGGUO

Enhanced capacitance trench capacitor

Method of forming enhanced capacitance trench capacitor

Embedded DRAM memory cell with additional patterning layer for improved strap formation

PEI CHENGWEN

Structure and method to form EDRAM on SOI substrate

Structure and method to form EDRAM on SOI substrate

INFINEON TECHNOLOGIES CORP

Method for manufacturing memory cell with trench capacitor

FANG SUNFEI

Shallow trench isolation for device including deep trench capacitors

BOOTH JR ROGER A

High density memory cells using lateral epitaxy

CHEN XIAOMENG

Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material

AQUILINO MICHAEL V

Sealed shallow trench isolation region