Inventor

NAEEM MUNIR D

US22 patents

⚠️ This page may combine multiple inventors who share the name “NAEEM MUNIR D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAEEM MUNIR D

IBM

Microscope specimen holder and grid arrangement for in-situ and ex-situ repeated analysis

Method of reducing RIE lag for deep trench silicon etching

Low pressure and low power C12 /HC1 process for sub-micron metal etching

STI formation for vertical and planar transistors

Shallow trench isolation structure compatible with SOI embedded DRAM

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Poly filled substrate contact on SOI structure

Method of preventing bridging between polycrystalline micro-scale features

Method of forming extruded structures from polycrystalline materials and devices formed thereby

Methods for etching tungsten stack structures

Reduced cap layer erosion for borderless contacts

Subground rule STI fill for hot structure

Embedded DRAM memory cell with additional patterning layer for improved strap formation

Poly filled substrate contact on SOI structure

Polycrystalline material with surface features projecting from a surface thereof

Method of forming nano-scale structures from polycrystalline materials and nano-scale structures formed thereby

CHENG KANGGUO

Enhanced capacitance trench capacitor

Method of forming enhanced capacitance trench capacitor

Embedded DRAM memory cell with additional patterning layer for improved strap formation

INFINEON TECHNOLOGIES AG

Method of deep trench formation with improved profile control and surface area

Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening

SIEMENS AG

Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing