Inventor

THAYER LARRY J

US23 patents

⚠️ This page may combine multiple inventors who share the name “THAYER LARRY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THAYER LARRY J

HEWLETT PACKARD DEVELOPMENT CO

Semiconductor memory device and system providing spare memory locations

Error correction algorithm selection based upon memory organization

Bit error rate reduction buffer

Defect management for a semiconductor memory system

Storage element for mitigating soft errors in logic

Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system

Memory controller

System and method for implementing a stride value for memory testing

Systems and methods for implementing a stride value for accessing memory

HEWLETT PACKARD CO

Polygon renderer which determines the coordinates of polygon edges to sub-pixel resolution in the X,Y and Z coordinates directions

Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size

Polygon span interpolator with main memory Z buffer

System-wide texture offset addressing with page residence indicators for improved performance

Corner buffer system for improved memory read efficiency during texture mapping

Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system

THAYER LARRY J

Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method

Systems and methods of selectively managing errors in memory modules

Bit error rate reduction buffer, method and apparatus

Repairing high-speed serial links

Memory module and method employing a multiplexer to replace a memory device

High speed interface for dynamic random access memory (DRAM)

AVAGO TECHNOLOGIES GENERAL IP

Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer

AVAGO TECHNOLOGIES ENTPR IP SINGAPORE PTE LTD

System and method for distribution analysis of stacked-die integrated circuits