Inventor

GULATI MANU

US86 patents

⚠️ This page may combine multiple inventors who share the name “GULATI MANU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GULATI MANU

APPLE INC

Secure bypass of low-level configuration in reconfiguration of a computing system

Security enclave processor for a system on a chip

Security enclave processor power control

System on a chip with always-on processor

Always-on audio control for mobile device

Unified addressable memory

Always-on audio control for mobile device

System on a chip with always-on processor

Always-on audio control for mobile device

Always-on audio control for mobile device

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Always-on audio control for mobile device

System on a chip with always-on processor

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Edge-triggered interrupt conversion in a system employing level-sensitive interrupts

Hierarchical feedback-controlled oscillator techniques

Always-on audio control for mobile device

Unified addressable memory

Storing address of spare in failed memory location

Storing address of spare in failed memory location

Method for waking a data transceiver through data reception

Mechanism for sharing private caches in a SoC

Timebase synchronization

Clock switching in always-on component

Memory power savings in idle display case

Serial wire debug bridge

Always-on audio control for mobile device

Storing address of spare in failed memory location

Interrupt timestamping

Race-free level-sensitive interrupt delivery using fabric delivered interrupts

BROADCOM CORP

Scalable cache coherent distributed shared memory processing system

Hypertransport/SPI-4 interface supporting configurable deskewing

Coherent shared memory processing system

Addressing scheme supporting variable local addressing and variable global addressing

System having two or more packet interfaces, a switch, and a shared packet DMA circuit

System having interfaces and switch that separates coherent and packet traffic

Apparatus and method to receive and align incoming data including SPI data in a buffer to expand data width by utilizing a single read port and single write port memory device

Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments

Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

Efficient routing of packet data in a scalable processing resource

Processing of received data within a multiple processor device

System having interfaces and switch that separates coherent and packet traffic

Packet data service over hyper transport link(s)

GULATI MANU

Efficient trace capture buffer management

Connectionless packet data transport over a connection-based point-to-point link

System on a chip (SOC) debug controllability

ADVANCED MICRO DEVICES INC

Method and apparatus for concurrently executing multiplication and iterative operations

SAUND GURJEET S

Bandwidth management

GUPTA ROHIT K

Memory management unit with prefetch ability

NUVIA INC

Hierarchical power management architecture for SoC-based electronic devices