Inventor
MCELHENY PETER J
US20 patents
⚠️ This page may combine multiple inventors who share the name “MCELHENY PETER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
13 patentsUS7277346B1Oct 2, 2007
Method and system for hard failure repairs in the field
ALTERA CORP34 citations91
US9576617B1Feb 21, 2017
Multiport memory element circuitry
ALTERA CORP9 citations82
US6127217AOct 3, 2000
Method of forming highly resistive interconnects
ALTERA CORP19 citations82
US6187634B1Feb 13, 2001
Process for making an EEPROM active area castling
ALTERA CORP13 citations73
US6038171AMar 14, 2000
Field emission erasable programmable read-only memory
ALTERA CORP12 citations73
US9634094B1Apr 25, 2017
Strain-enhanced transistors with adjustable layouts
ALTERA CORP2 citations71
US7902611B1Mar 8, 2011
Integrated circuit well isolation structures
ALTERA CORP3 citations62
US7812408B1Oct 12, 2010
Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers
ALTERA CORP4 citations62
US6265746B1Jul 24, 2001
Highly resistive interconnects
ALTERA CORP4 citations61
US9484411B1Nov 1, 2016
Integrated circuit and a method to optimize strain inducing composites
ALTERA CORP1 citations51
US8995177B1Mar 31, 2015
Integrated circuits with asymmetric transistors
ALTERA CORP1 citations51
US6624467B1Sep 23, 2003
EEPROM active area castling
ALTERA CORP0 citations51
US6472272B1Oct 29, 2002
Castled active area mask
ALTERA CORP1 citations51
VENKITACHALAM GIRISH
3 patentsUS8664725B1Mar 4, 2014
Strain enhanced transistors with adjustable layouts
VENKITACHALAM GIRISH12 citations81
US8627264B1Jan 7, 2014
Automated verification of transformational operations on a photomask representation
VENKITACHALAM GIRISH5 citations62
US8765541B1Jul 1, 2014
Integrated circuit and a method to optimize strain inducing composites
VENKITACHALAM GIRISH0 citations49