Inventor

KRISHNAN SIDDARTH A

US63 patents

⚠️ This page may combine multiple inventors who share the name “KRISHNAN SIDDARTH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRISHNAN SIDDARTH A

IBM

Forming a semiconductor structure for reduced negative bias temperature instability

Semiconductor device having dual metal gates and method of manufacture

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme

Integrated circuit with replacement gate stacks and method of forming same

Forming a semiconductor structure for reduced negative bias temperature instability

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

Replacement metal gate structures providing independent control on work function and gate leakage current

Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures

Gate effective-workfunction modification for CMOS

Nitrogen based plasma process for metal gate MOS device

Constrained nanosecond laser anneal of metal interconnect structures

Method of forming gate stack and structure thereof

Integrated circuit with replacement gate stacks and method of forming same

Integrated circuit with replacement gate stacks and method of forming same

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme

Semiconductor device having a gate stack with tunable work function

Gate stack with tunable work function

Semiconductor devices having different gate oxide thicknesses

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme

Forming a semiconductor structure for reduced negative bias temperature instability

Structure and method of Tinv scaling for high k metal gate technology

Concurrently forming nFET and pFET gate dielectric layers

Replacement gate with reduced gate leakage current

Shared metal gate stack with tunable work function

Field effect transistor stack with tunable work function

Field effect transistor stack with tunable work function

Shared metal gate stack with tunable work function

Shared metal gate stack with tunable work function

Field effect transistor stack with tunable work function

GLOBALFOUNDRIES INC

Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

Method and structure for III-V nanowire tunnel FETs

Field effect transistors having multiple effective work functions

Methods of forming multi-Vt III-V TFET devices

Integrated circuit having improved electromigration performance and method of forming same

Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor

Replacement channel TFET

Structures with thinned dielectric material

Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor

ANDO TAKASHI

Replacement gate with reduced gate leakage current

Replacement gate devices with barrier metal for simultaneous processing

CHUDZIK MICHAEL P

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

Structure and method of Tinv scaling for high κ metal gate technology

LI ZHENGWEN

Etch stop layer formation in metal gate process

KWON UNOH

Replacement metal gate structures providing independent control on work function and gate leakage current

BREIL NICOLAS

Non-volatile memory structure employing high-k gate dielectric and metal gate

ADAMS CHARLOTTE DEWAN

Semiconductor devices having different gate oxide thicknesses

BRODSKY MARYJANE

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

BU HUIMING

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

PARK DAE-GYU

Gate effective-workfunction modification for CMOS