Inventor
CAMAROTA RAFAEL C
US50 patents
⚠️ This page may combine multiple inventors who share the name “CAMAROTA RAFAEL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
18 patentsUS10673440B1Jun 2, 2020
Unified programmable computational memory and configuration network
XILINX INC32 citations94
US9911465B1Mar 6, 2018
High bandwidth memory (HBM) bandwidth aggregation switch
XILINX INC21 citations94
US8913455B1Dec 16, 2014
Dual port memory cell
XILINX INC20 citations93
US10963411B1Mar 30, 2021
Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
XILINX INC8 citations84
US10177107B2Jan 8, 2019
Heterogeneous ball pattern package
XILINX INC13 citations84
US11189338B1Nov 30, 2021
Multi-rank high bandwidth memory (HBM) memory
XILINX INC5 citations73
US10929331B1Feb 23, 2021
Layered boundary interconnect
XILINX INC4 citations73
US10502785B1Dec 10, 2019
Test network for a network on a chip and a configuration network
XILINX INC2 citations73
US9882562B1Jan 30, 2018
Rotated integrated circuit die and chip packages having the same
XILINX INC6 citations73
US9547034B2Jan 17, 2017
Monolithic integrated circuit die having modular die regions stitched together
XILINX INC2 citations73
US9083340B1Jul 14, 2015
Memory matrix
XILINX INC4 citations73
US10621132B1Apr 14, 2020
Auto address generation for switch network
XILINX INC4 citations71
US11201623B2Dec 14, 2021
Unified programmable computational memory and configuration network
XILINX INC0 citations63
US11169822B2Nov 9, 2021
Configuring programmable logic region via programmable network
XILINX INC1 citations63
US9204542B1Dec 1, 2015
Multi-use package substrate
XILINX INC2 citations62
US10784121B2Sep 22, 2020
Standalone interface for stacked silicon interconnect (SSI) technology integration
XILINX INC0 citations52
US10069497B2Sep 4, 2018
Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit
XILINX INC0 citations41
US10763862B1Sep 1, 2020
Boundary logic interface
XILINX INC0 citations35
ALTERA CORP
7 patentsUS7550994B1Jun 23, 2009
Programmable logic device with on-chip nonvolatile user memory
ALTERA CORP76 citations98
US7190190B1Mar 13, 2007
Programmable logic device with on-chip nonvolatile user memory
ALTERA CORP117 citations98
US7023238B1Apr 4, 2006
Input buffer with selectable threshold and hysteresis option
ALTERA CORP48 citations96
US7154297B1Dec 26, 2006
Programmable logic with programmable volatility
ALTERA CORP23 citations93
US7248070B1Jul 24, 2007
Method and system for using boundary scan in a programmable logic device
ALTERA CORP16 citations86
US7276935B1Oct 2, 2007
Input buffer with selectable threshold and hysteresis option
ALTERA CORP10 citations84
US7550995B1Jun 23, 2009
Method and system for using boundary scan in a programmable logic device
ALTERA CORP13 citations78
LATTICE SEMICONDUCTOR CORP
6 patentsUS6229336B1May 8, 2001
Programmable integrated circuit device with slew control and skew control
LATTICE SEMICONDUCTOR CORP77 citations95
US6294925B1Sep 25, 2001
Programmable logic device
LATTICE SEMICONDUCTOR CORP17 citations92
US6066977AMay 23, 2000
Programmable output voltage levels
LATTICE SEMICONDUCTOR CORP29 citations92
US6255847B1Jul 3, 2001
Programmable logic device
LATTICE SEMICONDUCTOR CORP6 citations74
US6462576B1Oct 8, 2002
Programmable logic device
LATTICE SEMICONDUCTOR CORP1 citations63
US6278311B1Aug 21, 2001
Method for minimizing instantaneous currents when driving bus signals
LATTICE SEMICONDUCTOR CORP2 citations63
NAT SEMICONDUCTOR CORP
5 patentsUS5336950AAug 9, 1994
Configuration features in a configurable logic array
NAT SEMICONDUCTOR CORP270 citations97
US5317209AMay 31, 1994
Dynamic three-state bussing capability in a configurable logic array
NAT SEMICONDUCTOR CORP41 citations95
US5298805AMar 29, 1994
Versatile and efficient cell-to-local bus interface in a configurable logic array
NAT SEMICONDUCTOR CORP114 citations95
US5341040AAug 23, 1994
High performance output buffer with reduced ground bounce
NAT SEMICONDUCTOR CORP30 citations94
US5319255AJun 7, 1994
Power up detect circuit for configurable logic array
NAT SEMICONDUCTOR CORP35 citations94
CAMAROTA RAFAEL C
4 patentsUS9026872B2May 5, 2015
Flexible sized die for use in multi-die integrated circuit
CAMAROTA RAFAEL C19 citations92
US8712718B1Apr 29, 2014
Predicting performance of an integrated circuit
CAMAROTA RAFAEL C11 citations81
US8539420B2Sep 17, 2013
Method and apparatus for self-annealing multi-die interconnect redundancy control
CAMAROTA RAFAEL C5 citations72
US8869088B1Oct 21, 2014
Oversized interposer formed from a multi-pattern region mask
CAMAROTA RAFAEL C2 citations62
ATMEL CORP
3 patentsUS5245227ASep 14, 1993
Versatile programmable logic cell for use in configurable logic arrays
ATMEL CORP186 citations99
US5488582AJan 30, 1996
Non-disruptive, randomly addressable memory system
ATMEL CORP31 citations93
US5805503ASep 8, 1998
Non-disruptive randomly addressable memory system
ATMEL CORP6 citations74
STRETCH INC
2 patentsCONCURRENT LOGIC INC
2 patentsADAPTIVE SILICON INC
2 patentsUS6292388B1Sep 18, 2001
Efficient and robust random access memory cell suitable for programmable logic configuration control
ADAPTIVE SILICON INC25 citations91
US6418045B2Jul 9, 2002
Efficient and robust random access memory cell suitable for programmable logic configuration control
ADAPTIVE SILICON INC19 citations83