Inventor

KITTL JORGE A

US51 patents

⚠️ This page may combine multiple inventors who share the name “KITTL JORGE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KITTL JORGE A

SAMSUNG ELECTRONICS CO LTD

Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

Method and system for performing analog complex vector-matrix multiplication

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the same

Methods of forming semiconductor devices, including forming a metal layer on source/drain regions

Crystalline multiple-nanosheet III-V channel FETs

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

Structure and method to achieve compressively strained Si NS

Method for forming low parasitic capacitance source and drain contacts

Monolithic multi-bit weight cell for neuromorphic computing

Ferroelectric-based memory cell usable in on-logic chip memory

Strained stacked nanosheet FETs and/or quantum well stacked nanosheet

Methods for varied strain on nano-scale field effect transistor devices

Sacrificial non-epitaxial gate stressors

Fabricating metal source-drain stressor in a MOS device channel

Low resistivity damascene interconnect

Confined semi-metal field effect transistor

Filling processes

Monolithic multi-bit weight cell for neuromorphic computing

Method of enabling sparse neural networks on memresistive accelerators

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Method and system for training of neural networks using continuously differentiable models

Giant spin hall-based compact neuromorphic cell optimized for differential read inference

Interconnects having long grains and methods of manufacturing the same

Bi-directional weight cell

Memory device with strong polarization coupling

FE-FET-based XNOR cell usable in neuromorphic computing

Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing

Methods of forming semiconductor devices, including forming a contact including an alkaline earth metal on a semiconductor layer, and related devices

Sacrificial epitaxial gate stressors

Interface layer for gate stack using O3 post treatment

Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions

Integrated circuit devices including strained channel regions and methods of forming the same

Integrated circuit devices including contacts and methods of forming the same

Composite piezoelectric capacitor

Interconnects having long grains and methods of manufacturing the same

Methods of forming a semiconductor layer including germanium with low defectivity

Method of providing reacted metal source-drain stressors for tensile channel stress

TEXAS INSTRUMENTS INC

CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes

Method of forming a silicide layer using metallic impurities and pre-amorphization

Method of forming a silicide layer using a pre-amorphization implant which is blocked from source/drain regions by a layer of photoresist

Method of forming a silicide layer using an angled pre-amorphization implant

Transistor having an improved salicided gate and method of construction

Method and system for improved nickel silicide

Method and system for improved nickel silicide

KITTL JORGE A

Structure and method to achieve large strain in NS without addition of stack-generated defects

Methods of forming semiconductor devices including conductive contacts on source/drains

Device contact structures including heterojunctions for low contact resistance

OBRADOVIC BORNA J

FinFET devices including recessed source/drain regions having optimized depths