Inventor

SEIDEL THOMAS E

26 patents

⚠️ This page may combine multiple inventors who share the name “SEIDEL THOMAS E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEIDEL THOMAS E

GENUS INC

Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition

Fully integrated process for MIM capacitors using atomic layer deposition

Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition

Processing chamber for atomic layer deposition processes

Vertically-stacked process reactor and cluster tool system for atomic layer deposition

Processing chamber for atomic layer deposition processes

Method and apparatus for flexible atomic layer deposition

Passivation method for improved uniformity and repeatability for atomic layer deposition and chemical vapor deposition

Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition

Massively parallel atomic layer deposition/chemical vapor deposition system

Methods and procedures for engineering of composite conductive films by atomic layer deposition

Methods and procedures for engineering of composite conductive films by atomic layer deposition

Methods and procedures for engineering of composite conductive by atomic layer deposition

SEIDEL THOMAS E

Limited dose atomic layer processes for localizing coatings on non-planar surfaces

Method and structure for nanoimprint lithography masks using optical film coatings

Method and structure for nanoimprint lithography masks using optical film coatings

Limited dose and angle directed beam assisted ALE and ALD processes for localized coatings on non-planar surfaces

SEMATECH INC

Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer

Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer

Staircase sidewall spacer for improved source/drain architecture

AT & T BELL LAB

Method of making and selectively doping isolation trenches utilized in CMOS devices

Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices

BELL TELEPHONE LABOR INC

Metallization for integrated circuits

Formation of multilayer dopant distributions in a semiconductor

AIXTRON INC

Transient enhanced atomic layer deposition

(unassigned)

PECVD and CVD processes for WNx deposition