Inventor

MIRHOSEINI AZALIA

US22 patents

⚠️ This page may combine multiple inventors who share the name “MIRHOSEINI AZALIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIRHOSEINI AZALIA

GOOGLE LLC

Generating integrated circuit floorplans using neural networks

Generating integrated circuit floorplans using neural networks

Device placement optimization with reinforcement learning

Mixture of experts neural networks

Generating integrated circuit placements using neural networks

Mixture of experts neural networks

Generating integrated circuit floorplans using neural networks

Device placement optimization with reinforcement learning

Generating integrated circuit floorplans using neural networks

Hierarchical device placement with reinforcement learning

Hierarchical device placement with reinforcement learning

Generating integrated circuit placements using neural networks

Generating integrated circuit placements using neural networks

Mixture of experts neural networks

Generating integrated circuit placements using neural networks

Computational graph optimization

Computational graph optimization

Synthesizing zero-loss low-power approximate DNN accelerators with large-scale search

Learned graph optimizations for compilers

Alignment cost for integrated circuit placement

MICROSOFT CORP

Optimizing task recommendations in context-aware mobile crowdsourcing

UNIV RICE WILLIAM M

Partitioned machine learning architecture