Inventor

MANDELBLAT JULIUS

IL20 patents

⚠️ This page may combine multiple inventors who share the name “MANDELBLAT JULIUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANDELBLAT JULIUS

INTEL CORP

Hybrid exclusive multi-level memory architecture with memory management

Cache allocation with code and data prioritization

Cache allocation with code and data prioritization

Methods and apparatus to increase boot performance by categorizing boot tasks

Device, system and method of managing a resource request

Method and apparatus of reporting memory bit correction

Performance monitoring in heterogeneous systems

Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures

Architecture for dynamic transformation of memory configuration

Posting weakly ordered transactions

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

Device, method and system to provide thread scheduling hints to a software process

System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms

Reducing back invalidation transactions from a snoop filter

Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach

Systems, apparatuses, and methods for resource bandwidth enforcement

Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Restricting clock signal delivery in a processor

YIGZAW THEODROS

Apparatus and method for implement a multi-level memory hierarchy

KURTS TSVIKA

G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine