Inventor
DAELLENBACH LUKAS
DE12 patents
⚠️ This page may combine multiple inventors who share the name “DAELLENBACH LUKAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
10 patentsUS10997350B1May 4, 2021
Semiconductor circuit design and unit pin placement
IBM10 citations85
US9418198B1Aug 16, 2016
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
IBM4 citations72
US11354478B2Jun 7, 2022
Semiconductor circuit design and unit pin placement
IBM0 citations62
US10936773B1Mar 2, 2021
Sink-based wire tagging in multi-sink integrated circuit net
IBM1 citations61
US10353841B2Jul 16, 2019
Optimizing routing of a signal path in a semiconductor device
IBM1 citations60
US12340161B2Jun 24, 2025
Multi-layer integrated circuit routing tool
IBM0 citations51
US10031996B2Jul 24, 2018
Timing based net constraints tagging with zero wire load validation
IBM1 citations51
US9727687B2Aug 8, 2017
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)
IBM0 citations51
US8930870B2Jan 6, 2015
Optimized buffer placement based on timing and capacitance assertions
IBM0 citations50
US7966597B2Jun 21, 2011
Method and system for routing of integrated circuit design
IBM1 citations50