Inventor

MOTWANI RAVI H

US50 patents

⚠️ This page may combine multiple inventors who share the name “MOTWANI RAVI H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOTWANI RAVI H

INTEL CORP

Use of error correction pointers to handle errors in memory

Recovery algorithm in non-volatile memory

Using read values from previous decoding operations to calculate soft bit information in an error recovery operation

Defective bit line management in connection with a memory access

Apparatus and method for mapping binary to ternary and its reverse

Error correction in memory

Technologies for providing efficient error correction with half product codes

Handling open circuits while writing data by moving them to the least vulnerable location in an error correction code codeword

Counter to locate faulty die in a distributed codeword storage system

Distributed concatenated error correction

Technologies for reducing latency in read operations

Apparatus and method for detecting and mitigating bit-line opens in flash memory

Apparatus and method for increasing resilience to raw bit error rate

Techniques for soft decision decoding of encoded data

Single-bit first error correction

Error correction in non—volatile memory

Defect management policies for NAND flash memory

Multi-level cell (MLC) non-volatile memory data reading method and apparatus

Scaling factors for hard decision reads of codewords distributed across die

Center read reference voltage determination based on estimated probability density function

Application of low-density parity-check codes with codeword segmentation

Non-uniform iteration-dependent min-sum scaling factors for improved performance of spatially-coupled LDPC codes

Techniques for correcting data errors in memory devices

Mitigating silent data corruption in error control coding

Apparatus, non-volatile memory storage device and method for detecting drift in non-volatile memory

Techniques to improve latency of retry flow in memory controllers

Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units

Self-configuring error control coding

Defective bit line management in connection with a memory access

Transfer of encoded data stored in non-volatile memory for decoding by a controller of a memory device

Overcoming error correction coding mis-corrects in non-volatile memory

Permutation of bit locations to reduce recurrence of bit error patterns in a memory device

One-sided soft reads

Application of low-density parity-check codes with codeword segmentation

Dynamic self-correction of message reliability in LDPC codes

Data scrambler for persistent memory

Error correction for dynamic data in a memory that is row addressable and column addressable

Multi-level cell (MLC) non-volatile memory data reading method and apparatus

Apparatus and method for mitigating loss of signal content

Identification of non-volatile memory die for use in remedial action

NAND memory management

Techniques to improve error correction using an XOR rebuild scheme of multiple codewords and prevent miscorrection from read reference voltage shifts

Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units

Memory controller with distribution transformer

Die-wise residual bit error rate (RBER) estimation for memories

MOTWANI RAVI H

Apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length

Storage drive with LDPC coding

Non-volatile memory error mitigation

Data storage and variable length error correction information

KALAVADE PRANAV

Reconstructing codewords using a side channel