Inventor · disambiguated record
Rajesh Arimilli
Also filed as: ARIMILLI RAJESH
8 granted patents·4 pending applications·17 citations·filing 2016–2025
80Inventor score
Top patents by PatentIndex Score
12 records- 0192US11689203B1Method and apparatus for symmetric aging of clock treesQUALCOMM INC·Filed 2022·Granted Jun 27, 2023·6 cites·20 claims
- 0287US10691195B2Selective coupling of memory to voltage rails based on operating mode of processorQUALCOMM INC·Filed 2018·Granted Jun 23, 2020·4 cites·30 claims
- 0380US10346574B2Effective substitution of global distributed head switch cells with cluster head switch cellsQUALCOMM INC·Filed 2017·Granted Jul 9, 2019·4 cites·12 claims
- 0475US10466766B2Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexersQUALCOMM INC·Filed 2017·Granted Nov 5, 2019·2 cites·27 claims
- 0570US10664006B2Method and apparatus for automatic switch to retention mode based on architectural clock gatingQUALCOMM INC·Filed 2018·Granted May 26, 2020·1 cites·17 claims
- 0661US11169593B2Selective coupling of memory to voltage rails for different operating modesQUALCOMM INC·Filed 2020·Granted Nov 9, 2021·0 cites·19 claims
- 0759US2025265402A1Topology of Integrated Clock Gate (ICGs) for Reduction of Sequential Depth by Coalescence of Flip-Flops Having a Low-Depth Fan-In Cone and a High-Depth Fan-Out ConeGOOGLE LLC·Filed 2025·Application pending·0 cites
- 0853US11604505B2Processor security mode based memory operation managementQUALCOMM INC·Filed 2020·Granted Mar 14, 2023·0 cites·24 claims
- 0952US2025172980A1Processor cluster configured to maximize utilization of a processor core electrically coupled directly to a power source and related methodsQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1048US11493986B2Method and system for improving rock bottom sleep current of processor memoriesQUALCOMM INC·Filed 2019·Granted Nov 8, 2022·0 cites·28 claims
- 1139US2021157382A1Method and system for waking up a cpu from a power-saving modeQUALCOMM INC·Filed 2019·Application pending·0 cites
- 1225US2017310312A1Clock spine with tap pointsQUALCOMM INC·Filed 2016·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →