Inventor

NGUYEN LE TRONG

US85 patents

⚠️ This page may combine multiple inventors who share the name “NGUYEN LE TRONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGUYEN LE TRONG

SEIKO EPSON CORP

Microprocessor architecture capable of supporting multiple heterogeneous processors

Microprocessor architecture capable of supporting multiple heterogeneous processors

System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer

High performance, superscalar-based computer system with out-of-order instruction execution

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

High-performance superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High performance, superscalar-based computer system with out-of-order instruction execution

Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

RISC microprocessor architecture implementing multiple typed register sets

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Superscalar risc instruction scheduling

Integrated structure layout and layout of interconnections for an integrated circuit chip

RISC microprocessor architecture implementing multiple typed register sets

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

Semiconductor floor plan for a register renaming circuit

System and method for handling load and/or store operations in a superscalar microprocessor

Apparatus and method for emulating a microelectronic device by interconnecting and running test vectors on physically implemented functional modules

Page printer controller including a single chip superscalar microprocessor with graphics functional units

RISC microprocessor architecture implementing multiple typed register sets

RISC microprocessor architecture implementing multiple typed register sets

SAMSUNG ELECTRONICS CO LTD

Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Multiprocessor operation in a multimedia signal processor

Single-instruction-multiple-data processing using multiple banks of vector registers

Execution unit for processing a data stream independently and in parallel

Shared bus system with transaction and destination ID

Load and store unit for a vector processor

Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions

(unassigned)

Single-instruction-multiple-data processing in a multimedia signal processor

INFINEON TECHNOLOGIES CORP

Data processing device with memory coupling unit