Inventor

LENTZ DEREK J

US71 patents

Patents

50 patents

US6611908B2Aug 26, 2003

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP83 citations99

US6272579B1Aug 7, 2001

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP120 citations99

US5649230AJul 15, 1997

System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching

SEIKO EPSON CORP161 citations99

US5560032ASep 24, 1996

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

SEIKO EPSON CORP193 citations99

US5539911AJul 23, 1996

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP133 citations99

US5440752AAug 8, 1995

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

SEIKO EPSON CORP170 citations99

US5961629AOct 5, 1999

High performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP135 citations98

US5560035ASep 24, 1996

RISC microprocessor architecture implementing multiple typed register sets

SEIKO EPSON CORP105 citations98

US5493687AFeb 20, 1996

RISC microprocessor architecture implementing multiple typed register sets

SEIKO EPSON CORP103 citations98

US5754800AMay 19, 1998

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

SEIKO EPSON CORP86 citations97

US5689720ANov 18, 1997

High-performance superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP90 citations97

US5533185AJul 2, 1996

Pixel modification unit for use as a functional unit in a superscalar microprocessor

SEIKO EPSON CORP116 citations97

US7739482B2Jun 15, 2010

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP26 citations96

US7162610B2Jan 9, 2007

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP21 citations96

US6986024B2Jan 10, 2006

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP28 citations96

US6959375B2Oct 25, 2005

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP19 citations96

US6954844B2Oct 11, 2005

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP29 citations96

US6948052B2Sep 20, 2005

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP23 citations96

US6915412B2Jul 5, 2005

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP25 citations96

US6735685B1May 11, 2004

System and method for handling load and/or store operations in a superscalar microprocessor

SEIKO EPSON CORP26 citations96

US6647485B2Nov 11, 2003

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP42 citations96

US6282630B1Aug 28, 2001

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

SEIKO EPSON CORP41 citations96

US6272619B1Aug 7, 2001

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP34 citations96

US6256720B1Jul 3, 2001

High performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP34 citations96

US6219763B1Apr 17, 2001

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

SEIKO EPSON CORP55 citations96

US6128723AOct 3, 2000

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP42 citations96

US6101594AAug 8, 2000

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP31 citations96

US6092181AJul 18, 2000

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP37 citations96

US6038654AMar 14, 2000

High performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP39 citations96

US6038653AMar 14, 2000

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

SEIKO EPSON CORP39 citations96

US5941979AAug 24, 1999

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

SEIKO EPSON CORP40 citations96

US5838986ANov 17, 1998

RISC microprocessor architecture implementing multiple typed register sets

SEIKO EPSON CORP42 citations96

US5832292ANov 3, 1998

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

SEIKO EPSON CORP38 citations96

US5682546AOct 28, 1997

RISC microprocessor architecture implementing multiple typed register sets

SEIKO EPSON CORP35 citations96

US5604865AFeb 18, 1997

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

SEIKO EPSON CORP50 citations96

US5515494AMay 7, 1996

Graphics control planes for windowing and other display operations

SEIKO EPSON CORP72 citations96

US5444853AAug 22, 1995

System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's

SEIKO EPSON CORP78 citations96

US6965987B2Nov 15, 2005

System and method for handling load and/or store operations in a superscalar microprocessor

SEIKO EPSON CORP43 citations95

US5564117AOct 8, 1996

Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units

SEIKO EPSON CORP39 citations95

US5499384AMar 12, 1996

Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device

SEIKO EPSON CORP82 citations95

US5481685AJan 2, 1996

RISC microprocessor architecture implementing fast trap and exception state

SEIKO EPSON CORP66 citations95

US5448705ASep 5, 1995

RISC microprocessor architecture implementing fast trap and exception state

SEIKO EPSON CORP79 citations95

US5394515AFeb 28, 1995

Page printer controller including a single chip superscalar microprocessor with graphics functional units

SEIKO EPSON CORP57 citations95

US6249856B1Jun 19, 2001

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP10 citations93

US7028161B2Apr 11, 2006

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

SEIKO EPSON CORP17 citations93

US6941447B2Sep 6, 2005

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP13 citations93

US6934829B2Aug 23, 2005

High-performance, superscalar-based computer system with out-of-order instruction execution

SEIKO EPSON CORP17 citations93

Showing the top 50 of 71 patents by PatentIndex Score.

LENTZ DEREK J

Patents

Microprocessor architecture capable of supporting multiple heterogeneous processors

Microprocessor architecture capable of supporting multiple heterogeneous processors

System for transferring data using value in hardware FIFO&#39;S unused data start pointer to update virtual FIFO&#39;S start address pointer for fast context switching

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

High performance, superscalar-based computer system with out-of-order instruction execution

RISC microprocessor architecture implementing multiple typed register sets

RISC microprocessor architecture implementing multiple typed register sets

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

High-performance superscalar-based computer system with out-of-order instruction execution

Pixel modification unit for use as a functional unit in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

RISC microprocessor architecture implementing multiple typed register sets

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

RISC microprocessor architecture implementing multiple typed register sets

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

Graphics control planes for windowing and other display operations

System and method for transferring data between a plurality of virtual FIFO&#39;s and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO&#39;s

System and method for handling load and/or store operations in a superscalar microprocessor

Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units

Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device

RISC microprocessor architecture implementing fast trap and exception state

RISC microprocessor architecture implementing fast trap and exception state

Page printer controller including a single chip superscalar microprocessor with graphics functional units

RISC microprocessor architecture implementing multiple typed register sets

RISC microprocessor architecture implementing multiple typed register sets

Polygon rasterization

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching

System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's